Intermec CK30 Service Manual page 80

Chapter 4 — Theory of Operation
SD31..0
SA25..0
SCAN_DREQ
SCAN_IRQ
Host CPU
I/F
DQM3..0
nOE
nWE
nPWE
RDY
RD/WR
FPGA_CS
HCR/PCI_CS
PCI_IRQ
SDCLK
SDCS0
SDCAS
SDRAS
BREQ, BGNT
CLK_OUT
FPGA_CLK
CK30 FPGA Block Diagram – PCI Bridge
70
Bus I/F Scanner I/F
DMA
BUFFER
IRQ
CTL
CTL
REGs
GPIO
Kypd
PCI
CTL
REGs
Local
CPU
I/F
Logic
SDRAM
Controller
DLL
CLK
Host I/F
Wrapper
The bridge maps PCI bus memory, IO, and configuration space into
PXA255 processor space in Memory Area 2. In this mode, the PXA255
functions as the initiator, reading data from and writing data to the
(target) PCI card as a memory-mapped device. The bridge also
incorporates an SDRAM controller so that it can function as an alternate
bus master. In this mode the PCI card is the initiator and the SDRAM in
Partition 0 is the target.
FIFO
DBP
COUNT
LOGIC
IMAGE
CAPTURE
STATE
MACHINE
BLUR
DETECT,
EXPOSURE
SENSE
BUS
ARBITER
PCI
IRQ CTL
WR FIFO
Initiator
Logic
RD FIFO
LogiCore
PCI Core
WR FIFO
Target
Logic
RD FIFO
DLL
(/2)
PCI Bridge
CK30 Handheld Computer Service Manual
SDBUF_D7..0
Scanner
DBP_HSYNC
SOS_VSYNC
I/F
TETH_DBP, SOS
TETH_PRESENT
ILLUM_LASEN_RTS
SPEED_RANGE_GDRD
SCAN_FLASH_EN
SCAN_TRIG*
IMAGER_PIXCLK
SCAN_LED
SCAN_LED_LOW
GPIO
USER_LED<2:1>
DOCK_TRIG*
VOL<2:0>
KEY_RET<7:0>
HCR_WR2*
HCR_WR5*
BATT_FAULT_IRQ
REQ#, GNT#
ACT#, PME#
CLKRUN#
INTA#
INTB#
IDSEL
AD31..0
C/BE#3..0
PAR
Mini-PCI Slot o
PERR#
SERR#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
RST#
PCLK
PCI_CLK