Fpga Download - Intermec CK30 Service Manual

Chapter 4 — Theory of Operation
SD31..0
SA25..0
SCAN_DREQ
SCAN_IRQ
Host CPU
I/F
DQM3..0
nOE
nWE
nPWE
RDY
RD/WR
FPGA_CS
PCI/HCR_CS
PCI_IRQ
SDCLK
SDCS0
SDCAS
SDRAS
BREQ, BGNT
CLK_OUT
FPGA_CLK
CK30 FPGA Block Diagram

FPGA Download

48
Bus I/F Scanner I/F
DMA
BUFFER
IRQ
CTL
CTL
REGs
GPIO
Kypd
PCI
CTL
REGs
Local
CPU
I/F
Logic
SDRAM
Controller
DLL
CLK
Host I/F
Wrapper
The FPGA is SRAM-based and must be downloaded at boot time and on
resume. Its image is stored in system flash and downloaded from the
PXA255 by a download driver using the FPGA parallel slave mode on data
lines SA_MD7:0. This process clearly must precede loading of any drivers
that expect to use the FPGA.
Software initiates the download by pulsing the FPGA_PGM* signal low to
clear the FPGA configuration space, waiting for its INIT status to go high
(alternate function of signal SCAN_DREQ), and starting the
FPGA_CLK.
FIFO
DBP
COUNT
IMAGE LOGIC
CAPTURE
STATE
MACHINE
BLUR
DETECT,
EXPOSURE
SENSE
BUS
ARBITER
PCI
IRQ CTL
WR FIFO
Initiator
Logic
RD FIFO
LogiCore
PCI Core
WR FIFO
Target
Logic
RD FIFO
DLL
(/2)
PCI Bridge
CK30 Handheld Computer Service Manual
SDBUF_D7..0
Scanner
DBP_HSYNC
SOS_VSYNC
I/F
TETH_DBP, SOS
TETH_PRESENT
ILLUM_LASEN_RTS
SPEED_RANGE_GDRD
SCAN_FLASH_EN
SCAN_TRIG*
IMAGER_PIXCLK
SCAN_LED
SCAN_LED_LOW
GPIO
USER_LED<2:1>
DOCK_TRIG*
VOL<2:0>
KEY_RET<7:0>
HCR_WR2*
HCR_WR5*
BATT_FAULT_IRQ
REQ#, GNT#
ACT#, PME#
CLKRUN#
INTA#
INTB#
IDSEL
AD31..0
C/BE#3..0
PAR
Mini-PCI Slot
PERR#
SERR#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
RST#
PCLK
PCI_CLK