Processor Core; Processor; System Clocks - Intermec CK30 Service Manual

Processor Core

Processor

System Clocks

CK30 Handheld Computer Service Manual
The CK30 platform is built around the Intel PXA255 "Cotulla" XScale
processor (U1). The low-end configurations of the CK30 (CK30AA and
CK30BA) use a 200MHz version of the PXA250 for cost reasons. The
high-end configuration (CK30CA) uses a 400MHz version of the part.
Refer to Intel documentation for detailed information on the PXA255
XScale processor operation and features.
All clocks in the system are derived from two oscillators built into the
PXA255 processor: a 3.6864MHz oscillator driven by crystal Y3 and a
32.768kHz oscillator driven by crystal Y2.
The 3.6864MHz clock is buffered and phase lock looped up in the
PXA255 to drive the CPU, memory, FPGA, and PXA255 internal
peripheral clocks. This oscillator is shut down during Suspend for power
savings. The 32.768KHz clock drives only the RTC. It is turned on by
software at boot time, and then is left on continuously to keep the RTC
running.
Oscillator Y1 is included as an alternate stuffing option for a 3.6864MHz
clock source. Its 3.3V output is divided down through R11 and R198 to
match the core voltage of the CPU – approx 1.30V. The oscillator is shut
down during Suspend by the PWR_EN signal. The major system clocks
are all derived from the PXA255 3.6864MHz oscillator and its associated
PLL:
CPU core 99.5MHz at boot time and resume. Boot code then
sets it to 199MHz (CK30AA and CK30BA). In the
case of the CK30CA, the boot code sets the CPU in
Turbo mode, doubling its speed to 398MHz.
CPU internal bus 99.5MHz.
SDCLK SDRAM clock, 49.77MHz at boot time and resume.
Boot code then sets it to 99.5MHz. An Automatic
Power Down (APD) power-saving feature in the
PXA255 memory controller is used to turn this clock
off when SDRAM is not being accessed.
FLASH_CLK 49.77MHz synchronous flash clock. This clock
defaults off at boot time and on resume and is
enabled by boot code only if the installed flash parts
are identified as K3C synchronous flash. Boot code
then initializes the memory controller to enable
synchronous mode.
Chapter 4 — Theory of Operation
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