Table of Contents
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INDEX
programming, 9-6–9-16
considerations, 9-16
pulsed output, 9-14–9-15
retriggering, 9-13–9-14
setup and hold times, 9-16
single maxcount mode, 9-13, 9-14–9-16
timer delay, 9-1
timing, 9-1
and BIU, 9-1
considerations, 9-16
TxOUT signal, 9-15
variable duty cycle output, 9-14–9-15
Timer Maxcount Compare Registers (TxCMPA,
TxCMPB), 9-11
Timers‚ See Timer/Counter Unit (TCU)
Trap exceptions, 2-43
Trap Flag (TF), 2-7, 2-9, 2-43, 2-48
T-state
and bus cycles, 3-9
and CLKOUT, 3-8
defined, 3-7
W
Wait states
and bus cycles, 3-13
and bus ready inputs, 3-13
and chip-selects, 6-15–6-17
and DRAM controllers, 7-1
and PCB accesses, 4-4
and READY input, 3-13
Word integer, defined, 11-7
World Wide Web, 1-6
Write bus cycle, 3-22
Z
Zero Flag (ZF), 2-7, 2-9, 2-23
Index-8
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