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CHIP-SELECT UNIT
Register Name:
Register Mnemonic:
Register Function:
15
U
1
7
Bit
Mnemonic
U17:10
Ending
Address
R2
Bus Ready
Disable
R1:0
Wait State
Value
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. Programming
U17:10 with values other than those shown in Table 6.3 on page 6-13 results in
unreliable chip-select operation. Reading this register (before writing it) enables
the chip-select; however, none of the programmable fields will be properly initial-
ized.
6-8
LCS Control Register
LMCS
Controls the operation of the LCS chip-select.
U
U
U
U
U
1
1
1
1
1
5
4
3
2
6
Reset
Bit Name
State
00H
X
3H
Figure 6-6. LMCS Register Definition
U
U
1
1
1
0
Function
Defines the ending address for the chip-select.
During memory bus cycles, U17:10 are
compared with the A17:10 address bits. A less
than result enables the LCS chip-select if
A19:18 are both zero. Table 6.3 on page 6-13
lists the only valid programming combinations.
When R2 is clear, bus ready must be active to
complete a bus cycle. When R2 is set, R1:0
control the number of bus wait states and bus
ready is ignored.
R1:0 define the minimum number of wait states
inserted into the bus cycle.
0
R
R
R
2
1
0
A1142-0A
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