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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Bit Name
Mnemonic
SFNM
Special
Fully
Nested
Mode
CAS
Cascade
Mode
LVL
Level-trigger
MSK
Interrupt
Mask
PM2:0
Priority
Level
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins
Interrupt Control Register (cascadable pins)
I0CON, I1CON
Control register for the cascadable external
interrupt pins
S
F
N
M
Reset
State
0
Set to enable special fully nested mode.
0
Set to enable cascade mode.
0
Selects the interrupt triggering mode:
0 = edge triggering
1 = level triggering.
The LVL bit must be set when external 8259As
are cascaded into the Interrupt Control Unit.
1
Clear to enable interrupts from this source.
111
Defines the priority level for this source.
INTERRUPT CONTROL UNIT
C
L
M
P
P
A
V
S
M
M
S
L
K
2
1
Function
0
P
M
0
A1215-A0
8-15
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