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INTERRUPT CONTROL UNIT
.
Register Name:
Register Mnemonic:
Register Function:
15
Bit
Mnemonic
LVL
Level-trigger
MSK
Interrupt
Mask
PM2:0
Priority
Level
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-5. Interrupt Control Register for Noncascadable External Pins
8-14
Interrupt Control Register (non-cascadable pins)
I2CON, I3CON
Control register for the non-cascadable external
internal interrupt pins
Reset
Bit Name
State
0
1
111
L
V
L
Function
Selects the interrupt triggering mode:
0 = edge triggering
1 = level triggering.
Clear to enable interrupts from this source.
Defines the priority level for this source.
0
M
P
P
P
S
M
M
M
K
2
1
0
A1214-A0
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