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Interrupt Vector Table, 2-39, 2-40
Interrupt-on-overflow trap (Type 4 exception),
2-44
Interrupts, 2-39–2-43
and CSU initialization, 6-6
controlling priority, 8-12
edge- and level-sensitive, 8-10
and external 8259As, 8-10
enabling cascade mode, 8-12
enabling special fully nested mode, 8-12
latency, 2-45
reducing, 3-28
latency and response times, 8-10, 8-11, 8-30
maskable, 2-43
masking, 8-3, 8-12, 8-16
priority-based, 8-17
multiplexed, 8-7
nesting, 8-4
NMI, 2-42
nonmaskable, 2-45
overview, 8-1, 8-2
priority, 2-46–2-49, 8-3
default, 8-3
resolution, 8-5, 8-6
processing, 2-39–2-42
reserved, 2-39
response time, 2-46
selecting edge- or level-triggering, 8-12
slave mode sources, 8-25
software, 2-45
timer interrupts, 9-16
types, 8-9, 8-26, 8-27
See also Exceptions, Interrupt Control Unit
INTn instruction, 2-45
Invalid opcode trap (Type 6 exception), 2-44
IRET instruction, 2-41
L
Latency‚ See Bus hold protocol‚ Direct Memory
Access (DMA) Unit‚ Interrupts
LEAVE instruction, A-7
Literature, ordering, 1-6
Local bus, 3-1, 3-41, 11-11
Long integer, defined, 11-7
Long real, defined, 11-7
M
Manuals, online, 1-5
Math coprocessing, 11-1
hardware support, 11-1
overview, 11-1
Memory
addressing, 2-28–2-36
operands, 2-28
reserved locations, 2-15
Memory devices‚ interfacing with, 3-6–3-7
Memory segments, 2-8
accessing, 2-5, 2-10, 2-11, 2-13
address
base value, 2-10, 2-11, 2-12
Effective Address (EA), 2-13
logical, 2-10, 2-12
offset value, 2-10, 2-13
overriding, 2-11, 2-13
physical, 2-3, 2-10, 2-12
and dynamic code relocation, 2-13
Memory space, 3-1–3-6
N
Normally not-ready signal‚ See Ready
Normally ready signal‚ See Ready
Numerics coprocessor fault (Type 16 exception),
2-44, 11-13
O
ONCE mode, 12-1
One-shot, code example, 9-17–9-23
Ordinal, defined, 2-37
Oscillator
external
and powerdown, 5-19
selecting crystal, 5-5
using canned, 5-6
internal crystal, 5-1–5-10
controlling gating to internal clocks,
5-18
operation, 5-2–5-3
selecting C
and L
1
5-6
OUTS instruction, A-2
Overflow Flag (OF), 2-7, 2-9, 2-44
INDEX
components, 5-3–
1
Index-5
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