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DIRECT MEMORY ACCESS UNIT
Register Name:
Register Mnemonic:
Register Function:
15
D
D
D
M
D
I
E
E
N
M
C
C
Bit
Bit Name
Mnemonic
TC
Terminal
Count
INT
Interrupt
SYN1:0
Synchroni-
zation Type
P
Relative
Priority
IDRQ
Internal
DMA
Request
Select
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
Figure 10-11. DMA Control Register (Continued)
10-16
DMA Control Register
DxCON
Controls DMA channel parameters.
S
S
S
T
I
M
D
I
C
N
E
E
N
T
M
C
C
Reset
State
X
Set TC to terminate transfers on Terminal Count. This bit
is ignored for unsynchronized transfers (that is, the DMA
channel behaves as if TC is set, regardless of its
condition).
X
Set INT to generate an interrupt request on Terminal
Count. The TC bit must be set to generate an interrupt.
XX
Selects channel synchronization:
SYN1 SYN0
0
0
1
1
X
Set P to select high priority for the channel; clear P to
select low priority for the channel.
X
Set IDRQ to select internal DMA requests and ignore
the external DRQ pin. Clear IDRQ to select the DRQ pin
as the source of DMA requests. When IDRQ is set, the
channel must be configured for source-synchronized
transfers (SYN1:0 = 01).
S
S
P
I
Y
Y
D
N
N
R
1
0
Q
Function
Synchronization Type
0
Unsynchronized
1
Source-synchronized
0
Destination-synchronized
1
Reserved (do not use)
0
C
S
W
H
T
O
G
R
R
T
D
A1180-0A
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