Intel 80C186EA User Manual page 13

CONTENTS
Figure
3-15 Generating a Normally Not-Ready Bus Signal ...........................................................3-16
3-16 Generating a Normally Ready Bus Signal ..................................................................3-17
3-17 Normally Not-Ready System Timing ..........................................................................3-18
3-18 Normally Ready System Timings ...............................................................................3-19
3-19 Typical Read Bus Cycle .............................................................................................3-21
3-20 Read-Only Device Interface .......................................................................................3-22
3-21 Typical Write Bus Cycle..............................................................................................3-23
3-22 16-Bit Bus Read/Write Device Interface .....................................................................3-24
3-23 Interrupt Acknowledge Bus Cycle...............................................................................3-26
3-24 Typical 82C59A Interface ...........................................................................................3-27
3-25 HALT Bus Cycle .........................................................................................................3-30
3-26 Returning to HALT After a HOLD/HLDA Bus Exchange ............................................3-31
3-27 Returning to HALT After a Refresh Bus Cycle ...........................................................3-32
3-28 Returning to HALT After a DMA Bus Cycle ................................................................3-33
3-29 Exiting HALT (Powerdown Mode) ..............................................................................3-34
3-30 Exiting HALT (Active/Idle Mode).................................................................................3-35
3-31 DEN and DT/R Timing Relationships .........................................................................3-36
3-32 Buffered AD Bus System............................................................................................3-37
3-33 Qualifying DEN with Chip-Selects ..............................................................................3-38
3-34 Queue Status Timing..................................................................................................3-41
3-35 Timing Sequence Entering HOLD ..............................................................................3-42
3-36 Refresh Request During HOLD ..................................................................................3-44
3-37 Latching HLDA ...........................................................................................................3-45
3-38 Exiting HOLD..............................................................................................................3-46
4-1 PCB Relocation Register..............................................................................................4-2
5-1 Clock Generator ...........................................................................................................5-1
5-2 Ideal Operation of Pierce Oscillator..............................................................................5-2
5-3 Crystal Connections to Microprocessor........................................................................5-3
5-4 Equations for Crystal Calculations................................................................................5-4
5-5 Simple RC Circuit for Powerup Reset ..........................................................................5-7
5-6 Cold Reset Waveform ..................................................................................................5-8
5-7 Warm Reset Waveform ................................................................................................5-9
5-8 Clock Synchronization at Reset..................................................................................5-10
5-9 Power Control Register ..............................................................................................5-12
5-10 Entering Idle Mode .....................................................................................................5-13
5-11 HOLD/HLDA During Idle Mode...................................................................................5-14
5-12 Entering Powerdown Mode ........................................................................................5-17
5-13 Powerdown Timer Circuit ...........................................................................................5-18
5-14 Power-Save Register .................................................................................................5-20
5-15 Power-Save Clock Transition .....................................................................................5-21
6-1 Common Chip-Select Generation Methods..................................................................6-2
6-2 Chip-Select Block Diagram...........................................................................................6-3
6-3 Chip-Select Relative Timings .......................................................................................6-4
6-4 UCS Reset Configuration .............................................................................................6-5
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FIGURES
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