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T
, T
and T
define the maximum data access requirements for the memory device. These
OE
ACC
CE
device parameters must be less than the value calculated in the equation column. An equal to or
greater than result indicates that wait states must be inserted into the bus cycle.
T
determines the maximum time the memory device can float its outputs before the next bus
DF
cycle begins. A T
value greater than the equation result indicates a buffer fight. A buffer fight
DF
means two (or more) devices are driving the bus at the same time. This can lead to short circuit
conditions, resulting in large current spikes and possible device damage.
T
cannot be lengthened (other than by slowing the clock rate). To resolve a buffer fight con-
RHAX
dition, choose a faster device or buffer the AD bus (see "Buffering the Data Bus" on page 3-36).
CLKOUT
S2:0
ALE
A19:16
A15:8
BHE
RFSH
A15:0
[AD7:0]
RD
DT/R
DEN
T1
T2
Status Valid
Address Valid
Address
Valid
Figure 3-19. Typical Read Bus Cycle
BUS INTERFACE UNIT
T3
T4
A18:16 = 0, A19=Valid Status
Valid
Data
Valid
A1046-0A
3-21
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