Address, D, Control, Q, And K-Clocks Topologies; Tcam/Sram/Coprocessor Interface Guidelines (Address, D, Control, Q, And K-Clocks) - Intel IXP28XX Manual

IXP28XX Network Processor
QDR SRAM
Figure 45.
Table 33.
4.7.1.1.2
82
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Address, D, CONTROL, Q, and K-Clocks Topologies

®
Intel IXP2800 Driver
Address
D, Parity-Out
RPE#, WPE#, BWE#
K/K#-Clocks
®
Intel IXP2800 Receiver
Q, Parity-In
(On-Die Termination 50Ω)
Table 33 provides routing guidelines for the TCAM/SRAM/coprocessor interface base card.
TCAM/SRAM/Coprocessor Interface Guidelines (Address, D, CONTROL, Q, and K-
Clocks)
Parameter
Signal Group
Topology
Reference Plane
Characteristic Trace Impedance
Nominal Trace Width
Nominal Trace Separation for group
Group spacing
IXP28XX breakout guideline
A or B trace length
C, C#, CIN, and CIN# Clocks Signals
Figure 46 illustrates the topologies for the C, C#, CIN, and CIN# clocks.
MICTOR
Connector
A
MICTOR
Connector
A
Routing Guideline
TCAM/SRAM/coprocessor Address, D, CONTROL, Q, and
K-Clocks
Point-to-Point
Ground
50 Ω ±5%
5 mils
8 to 15 mils
Isolation from non-QDR and non-group-related signals is
20 mils.
3.5 mils with 4 mil space for a maximum of 400 mils
Maximum = 5.0 inches (IXP28XX pin to Mictor* pin)
The trace length from ball-to-ball should be within 25 mils.
Hardware Design Guide
B3960-01