Di/Dt Droop Analysis Results; Recommendations From Droop Analysis - Intel IXP28XX Manual

2.5.1
2.5.2
Hardware Design Guide
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di/dt Droop Analysis Results

An exhaustive droop analysis was performed using an Intel system validation platform. The goal of
analysis was to correlate the measured power-on di/dt with the theoretical design values. A detailed
model of the system board, power delivery circuit and package were developed and simulated
using the theoretical di/dt transient events to predict the voltage droop measured at the pins of the
device. Several correlation analysis were performed to ensure the integrity of the models. Once the
models were validated the simulation results were compared with measured results from the
system validation platform. The final step of the analysis was to perform a sensitivity analysis by
varying the di/dt stimulus to match the simulated results to the measured results.
The outcome of the analysis is the transient curve shown
the findings of the correlation study:
•
The First Droop magnitude is 34 mV (tr1 = 6 cycles, tr2 = 9 cycles, and tr3 = 1 cycle), which
occurs at 8 ns after transient is applied.
— The magnitude and time of the first droop depends on the combination of tr1 and tr2
transient events.
•
The Second Droop magnitude is 78.4 mV, which occurs at 0.67 µs after transient.
— The second droop depends on when the Microengines come out of reset, specifically how
much time this occurs after PLL locks and power starts decreasing.
•
The Third Droop magnitude is 67.6 mV, which occurs between 10.1 – 13.1 µs after transient.
— Assuming Voltage Regulator Bandwidth = 10 KHz.
— Cbulk is only 50% of its total capacitance.
— I_final = 10.703 A (10% more than 9.73 A measured value).
— The number of clock cycles for tr3 does not impact the third droop.
— The amount of final current load and Cbulk will impact the amplitude of the third droop.
•
The first, second, and third droops are not affected by the duration of tr3.

Recommendations From Droop Analysis

There are two major recommendations from the correlation study:
•
Increase the system board cavity (under the processor) capacitors to address the second droop
amplitude. To reduce the magnitude of the second droop in the 0.67us timeframe, sufficient
decoupling capacitors should be placed under the processor; refer to
•
Increase bulk capacitors to address the third droop amplitude. As shown in
will decrease after the PLL locks and the MicroEngines are taken out of reset, therefore
sufficient bulk capacitance is required to ride through the ~1uS high current transient event.
IXP28XX Network Processor
Power Ratings and Requirements
Figure 6. The following items summarize
Figure 2.
Figure 6 the current
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