Related Manuals for Intel Processor IQ80332
Summary of Contents for Intel Processor IQ80332
- Page 1 ® Intel IQ80332 I/O Processor Evaluation Platform Board Manual September 2004 Document Number: 274069-001US...
- Page 2 TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd. *Other names and brands may be claimed as the property of others.
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Page 3: Table Of Contents
Document Purpose and Scope ... 9 Other Related Documents ... 9 Electronic Information ... 10 Component References ... 10 Terms and Definitions ... 11 ® Intel 80332 I/O Processor ...12 ® Intel IQ80332 I/O Processor Evaluation Platform Board Features ... 14 Getting Started... 15 Kit Content ... - Page 4 Board Support Package (BSP) Examples ... 48 ® 4.3.1 Intel 80332 I/O Processor Memory Map ... 48 4.3.2 RedBoot* Intel 4.3.3 RedBoot Intel 4.3.4 RedBoot 80332 DDR Memory Initialization Sequence ... 50 IQ80321 and IQ80332 Comparisons... 51 S7A1-1: PCI-X Bus A Speed Enable corresponding to signal...
- Page 5 Overview ... 67 B.9.2 Hardware and Software Breakpoints ... 67 B.9.2.1 Software Breakpoints ... 67 B.9.2.2 Hardware Breakpoints ... 67 B.9.3 C.9.3 Exceptions/Trapping ... 68 Document Number: 274069-001US ® Intel IQ80332 I/O Processor Evaluation Platform Board Manual September, 2004 Contents...
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Page 6: Board Form Factor ..................................................................................................................... 26
10 RESET Sources ... 37 11 Default Switch Setting Switch S7A1 ... 38 12 Flash Connection to Peripheral Bus ... 46 ® 13 Intel 80332 I/O Processor Memory Map... 48 ® 14 Intel 80332 I/O Processor Hardware Setup Flow Chart ... 55 15 Software Flow Diagram ... - Page 7 38 Jumper J7B4: Settings and Operation Mode ...44 39 Jumper J9D3: Descriptions... 44 40 Jumper J9D3: Settings and Operation Mode...44 41 Peripheral Bus Memory Map ... 47 ® 42 Intel IQ80321 Evaluation Platform Board and Intel board Comparisons51 43 Related Documents ...53 Document Number: 274069-001US ® Intel IQ80332 I/O Processor Evaluation Platform Board Manual ®...
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Page 8: Revision History
® Intel IQ80332 I/O Processor Evaluation Platform Board Manual Contents Revision History Date Revision Description 27 September 2004 Initial Release. September, 2004 Document Number: 274069-001US... -
Page 9: Introduction
This document describes the Intel using DDR-II 400 MHz SDRAM. The Intel intelligent I/O development. The 80332 is a multi-function device that integrates the Intel XScale® core (ARM* architecture compliant) with intelligent peripherals including a PCI Express bus application bridge. -
Page 10: Electronic Information
IQ80332 I/O Processor Introduction Electronic Information Table 2. Electronic Information Support Type The Intel World-Wide Web (WWW) Location: Customer Support (US and Canada): Component References Table 3 provides additional information on the major components of 80332. Table 3. Component Reference... -
Page 11: Terms And Definitions
In-Circuit Emulator – A piece of hardware used to mimic all the functions of a microprocessor. I/O processor Joint Test Action Group – A hardware port supplied on Intel XScale® microarchitecture JTAG evaluation boards used for in-depth testing and debugging. -
Page 12: Intel ® 80332 I/O Processor
Introduction ® Intel 80332 I/O Processor About the 80332. The 80332 is a multi-function device that combines the Intel XScale® core with intelligent peripherals, and integrates two PCI Express-to-PCI Bridges. The 80332 consolidates into a single system: • Intel XScale® core. -
Page 13: Intel ® 80332 I/O Processor Block Diagram
® Intel IQ80332 I/O Processor Introduction ® Figure 1. Intel 80332 I/O Processor Block Diagram Evaluation Platform Board Manual... -
Page 14: Intel ® Iq80332 I/O Processor Evaluation Platform Board Features
• 1 64-bit PCI-X connector - 133 MHz. • 1 64 bit 100 MHz PCI-X • Intel(R) 82545EM Gigabit Ethernet Controller also on the 100 MHz PCI. Dual RJ11 serial port connectors. The 80332 has two integrated UART serial ports which are 16550 compatible. -
Page 15: Getting Started
Getting Started The 80332 is a software development environment for IQ80332. Software updates and additional offerings from vendors can change frequently. To keep up-to-date, please visit http://www.intel-ioprocessortools.com/kshowcase/view for the latest updates. Kit Content The 80332 Kit contains the following items: •... -
Page 16: Power Requirements
® Intel IQ80332 I/O Processor Getting Started 2.2.2 Power Requirements The 80332 requires a 3.3 V supply coming through the PCI Express primary connector. Plug the board into a desktop with a PCI Express slot. The 80332 has an auxiliary power receptacle (J1A1, see is used to power the secondary PCI-X slot. -
Page 17: Factory Settings
• TimeSys* Linux* RTOS • Accelerated Technology Inc.*, Nucleus Plus* RTOS and Development Tools Please contact your Intel representative for the latest updates or visit http://www.intel-ioprocessortools.com/kshowcase/view. 2.4.2 Contents of the Flash The production version of the board contains an image for RedHat RedBoot* target monitor. -
Page 18: Target Monitors
® Intel IQ80332 I/O Processor Getting Started Target Monitors 2.5.1 RedHat RedBoot RedBoot* is an acronym for “RedHat Embedded Debug and Bootstrap”, and is the standard embedded system debug/bootstrap environment from RedHat, replacing the previous generation of debug firmware: CygMon and GDB stubs. It provides a bootstrap environment for a range of embedded operating systems, such as embedded Linux and eCos*, and includes facilities such as network downloading and debugging. -
Page 19: Host Communications Examples
The host computer, when loaded with the proper software can communicate with the board. Figure 3. JTAG Debug Communication Laptop computer Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Getting Started (Figure 2). Please note that the evlaution (Figure 3). Please note that the evaluation... -
Page 20: Network Communication
® Intel IQ80332 I/O Processor Getting Started 2.6.3 Network Communication Using a standard network connection, the user can communicate with the board via the ethernet port. Redboot also allows the user to remotely boot the platform using a BOOTP server through the network Connection. -
Page 21: Gnupro Gdb/Insight
“A1” on the LEDs. When the final state of “A1” does not occur, reset the processor again. The time for reset is approximately 1 or 2 seconds. Win32 on Host Connecting with HyperTerminal. Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Getting Started... - Page 22 ® Intel IQ80332 I/O Processor Getting Started To bring up a HyperTerminal session on a Win32 platform: Go to Start, Programs, Accessories, Communications, HyperTerminal • HyperTerminal setup screens: — “Connection Description” Panel: • Enter name. — “Connect To” Panel: •...
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Page 23: Connecting With Gdb
• Set breakpoint at main. (GDB) continue • Start the program using 'continue' verse the usual 'run'. • Program hits break at main() and wait. To be supplied separately. Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Getting Started... - Page 24 ® Intel IQ80332 I/O Processor Getting Started This Page Left Intentionally Blank Evaluation Platform Board Manual...
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Page 25: Hardware Reference Section
Local Bus RS-232 RS-232 GPIOs JTAG Evaluation Platform Board Manual DDR II 400 DDR SDRAM Battery Backup Intel® PCI-X 2.0 Bus Slot (266MHz) 80332 Processor PCI-X Bus IOP (100 MHz) X8 Edge Connector ® Intel IQ80332 I/O Processor Hardware Reference Section... -
Page 26: Board Form-Factor/Connectivity
The 80332 has two serial ports and one RJ-45 Ethernet port. The 80332 has one JTAG port compliant with ARM Multi-ICE 20-pin connector standard. The JTAG is targeted for the Intel XScale® core and the CPLD, and is used for software debug purposes. -
Page 27: Power
Power The 80332 draws power from the PCI Express bus. The power requirements for the 80332 are shown Table 7 below. The numbers do not include the power required by a PCI-X card mounted on the expansion slot. Table 7. Power Features Voltage Rail +3.3 V... -
Page 28: Memory Subsystem
® Intel IQ80332 I/O Processor Hardware Reference Section Memory Subsystem The Memory Controller of 80332 controls the DDR SDRAM memory subsystem. It features pro- grammable chip selects and support for error correction codes (ECC). The memory controller can be configured for DDR SDRAM at 333 MHz and DDR-II at 400 MHz. The memory controller supports pipelined access and arbitration control to maximize performance. -
Page 29: Flash Memory Requirements
Table 8. Flash Memory Requirements IQ80332 Total Flash size is 8 MB 80332 Flash technology is based on Intel StrataFlash 80332 Flash uses a 16-bit interface 80332 Flash utilizes the 80332 Peripheral Bus 80332 May be programmed using the PCI-X interface – Flash Recovery Utility (FRU) Utility 80332 May be programmed using a RAM based software target monitor –... -
Page 30: Interrupt Routing
® Intel IQ80332 I/O Processor Hardware Reference Section Interrupt Routing 80332 Interrupt routing. Table 9. External Interrupt Routing to Intel ® 80332 I/O Processor Interrupt HPI# S_INTA# S_INTB# S_INTC# S_INTD# P_INTA# P_INTB# P_INTC# P_INTD# System Resource Temperature Sensor, Header PCI-X Slot INTB#, Header... -
Page 31: Intel ® Iq80332 I/O Processor Evaluation Platform Board Peripheral Bus
The 80332 populates the peripheral bus as depicted by ® Figure 7. Intel IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology Intel® 80332 I/O Processor PBI Bus PC 104 Connector The devices on the bus include Flash ROM, audio buzzer, CPLD, HEX display, NVSRAM, and rotary switch. -
Page 32: Flash Rom
IQ80332 I/O Processor Hardware Reference Section 3.6.1 Flash ROM Table 11. Flash ROM Features Flash is an Intel StrataFlash Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 8. Flash Connection on Peripheral Bus Intel Description ®... -
Page 33: Uart
The audio buzzer’s for more details. Section 4.2.2, “Peripheral Bus Memory Map” on for more details on addressing the rotary switch. Description Figure ® Intel IQ80332 I/O Processor Hardware Reference Section for more details. Section 4.2.2, “Peripheral Bus Section 4.2.2,... -
Page 34: Battery Status
® Intel IQ80332 I/O Processor Hardware Reference Section 3.6.7 Battery Status A CPLD on the IQ80332 Bus Memory Map” on page 47 Table 13. Battery Status Buffer Requirements Read/ Write Battery Present Battery Charged Battery Discharged Battery Enable Reserved provides the following status for the battery. -
Page 35: Debug Interface
Console Serial Port The platform has two serial ports for debug purposes as described in I/O Processor Evaluation Platform Board Peripheral Bus” on page Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Hardware Reference Section ® Section 3.6, “Intel IQ80332... -
Page 36: Jtag Debug
® Intel IQ80332 I/O Processor Hardware Reference Section 3.7.2 JTAG Debug The 80332 has a 20-pin JTAG connector (J7D2) that is in compliant with ARM Multi-ICE guidelines. 3.7.2.1 JTAG Port Figure 9. JTAG Port Pin-out VTref Vsupply nTRST RTCK nSRST... -
Page 37: Board Reset Scheme
Debounce Power Delay JTAG Voltage Monitor Evaluation Platform Board Manual Table 14 Description DDR II SDRAM M_RST# RESETIN B_RST# PWRDELAY Intel® 80332 I/O Processor A_RST# TRST TRST CPLD SRST PWRGD Isolation Pwrgood PCI-E Con ® Intel IQ80332 I/O Processor Hardware Reference Section list the reset schemes for the 80332. -
Page 38: Switches And Jumpers
® Intel IQ80332 I/O Processor Hardware Reference Section Switches and Jumpers 3.9.1 Switch Summary Please note that the term ‘open’ refers to the individual pin of switch S7A1 being pushed in at bottom (small dot on pin away from the ‘open’ label on the switch). The term ‘closed’ refers to the pin being pushed in at the top. -
Page 39: Jumper Summary
Description Section 19, “J2D2 GPIO Header Definition” on page 39 Signal Signal GPIO5 GPIO7 GPIO4 GPIO6 GPIO3 ® Intel IQ80332 I/O Processor Hardware Reference Section Factory Default Open 1-2, 3-4 Open Open Section 2.2.2, “Power Requirements” shows the GPIO Signal... -
Page 40: Detail Descriptions Of Switches/Jumpers
S7A1-2: Reset IOP core corresponding to signal name PBI_AD5 RESET MODE is latched at the de-asserting edge of P_RST# and it determines when the 80332 is held in reset until the Intel XScale® core Reset bit is cleared in the PCI Configuration and Status Register. Table 22. -
Page 41: Switch S7A1-3: Retry: Settings And Operation Mode
Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode S7A1-6 Open Hot Plug on Bus B Enabled Closed Disables Hot Plug on Bus B(Default mode) Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Hardware Reference Section Operation Mode Operation Mode Operation Mode Operation Mode... -
Page 42: Switch S7A1- 10: Smbus Manageability Address Bit 1 Corre
® Intel IQ80332 I/O Processor Hardware Reference Section 3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 corresponding to signal name PBI_AD17 This allows 80332 to address SMBus Slave Address bit 0 (PBI_A17). Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode... -
Page 43: Jumper J7D1: Flash Bit-Width
3.9.6.5 Jumper J7D1: Flash bit-width ® The Intel IQ80332 I/O processor evaluation platform board expects an 8-bit Flash enable. Table 31. Jumper J7D1: Descriptions Jumper J7D1 8-bit Flash Enable Table 32. Jumper J7D1: Settings and Operation Mode Pins Enables 16-bit Flash 8-bit Flash (default mode) 3.9.6.6... -
Page 44: Jumper J7B4: Smbus Header
® Intel IQ80332 I/O Processor Hardware Reference Section 3.9.6.8 Jumper J7B4: SMBus Header Table 37. Jumper J7B4: Descriptions Jumper J7B4 SMBus Header Table 38. Jumper J7B4: Settings and Operation Mode J7B4 Pins 1, 2 Connects SM_SCLK to EEPROM U7B2 (Default Mode). -
Page 45: Software Reference
See the Intel 80332 I/O Processor Design Guide, section 8, table 34 for supported DDR333 and DDR-II configurations. For all registers relating to DRAM and other MCU related registers, see the Intel Processor Developer’s Manual. Components on the Peripheral Bus The 80332 has a peripheral bus which contains the following peripheral devices: •... -
Page 46: Flash Rom
Flash Connection to Peripheral Bus Intel Under normal operation, the very first instruction access by the Intel XScale® core begins at location 0x0 on the 80332 Internal Bus. By default, address 0x0 is pointing to PCE0 where flash is located. -
Page 47: Peripheral Bus Memory Map
64 KB 8-bit 64 KB 8-bit 64 KB 8-bit 64 KB 8-bit 64 KB 8-bit ® Intel IQ80332 I/O Processor Software Reference Description Flash memory (re-mapped) Product Code Board Stepping CPLD Firmware Revision Discrete LEDs Hex Display Left Hex Display Right... -
Page 48: Board Support Package (Bsp) Examples
® Intel IQ80332 I/O Processor Software Reference Board Support Package (BSP) Examples Examples provided in this section are based on the RedHat* RedBoot software running on the IQ80332. ® 4.3.1 Intel 80332 I/O Processor Memory Map Figure 13 depicts the memory space for the 80332 (before RedBoot boots): ®... -
Page 49: Redboot* Intel ® 80332 I/O Processor Memory Map
PCE1# - Uncached Unused Unused 0xF00 0000 Cache flush Unused PMMR - Intel 0xFFF0 0000 Registers. Please see Chapter 17 of the Intel Processor Developer’s Manual for more details. ® 80332 I/O Processor Files ® Intel IQ80332 I/O Processor Software Reference Description ®... -
Page 50: Redboot 80332 Ddr Memory Initialization Sequence
® Intel IQ80332 I/O Processor Software Reference 4.3.4 RedBoot 80332 DDR Memory Initialization Sequence In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be written to with a known value. This process requires 64-bit writes to the entire DDR memory intended for use. -
Page 51: Iq80321 And Iq80332 Comparisons
Bus with chip-enable 0 (PCE0) Serial Debug Port Two UARTs integrated within the 80332. Network Debug Port Intel® 82545EM GbE on the 100 MHz PCI-X bus Intel® 82544 GbE on the PCI-X bus Rotary Switch Same LED HEX Display Same... - Page 52 ® Intel IQ80332 I/O Processor IQ80321 and IQ80332 Comparisons This Page Left Intentionally Blank Evaluation Platform Board Manual...
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Page 53: Getting Started And Debugger
This appendix pertains to Code|Lab version 2.3 and later which uses Microsoft's Visual Studio .NET. For Code|Lab version 2.2 and earlier, refer to appendix B. For more detailed information on JTAG and the 80332, please see the Intel JTAG Support White Paper. -
Page 54: Related Web Sites
® Intel IQ80332 I/O Processor Getting Started and Debugger B.1.4 Related Web Sites • Macraigor: http://www.ocdemon.net/ • http://developer.intel.com/design/intelxscale/dev_tools/021022/index.htm • http://developer.intel.com/design/iio/ • http://developer.intel.com/design/iio/papers/273961.htm Evaluation Platform Board Manual... -
Page 55: Setup
Setup B.2.1 Hardware Setup Figure 14 and the rest of the Intel set up the hardware. • Connect the Raven to the host via the parallel port and to the evaluation board via the 20-pin JTAG connector. Note: The parallel port must be configured to EPP mode for the Macraigor Raven to work properly. -
Page 56: Software Setup
® Intel IQ80332 I/O Processor Getting Started and Debugger B.2.2 Software Setup ATI Code|Lab is a plug-in to Microsoft Visual Studio .NET, therefore Microsoft Visual Studio .NET must already be loaded on the system. To load ATI Code|Lab, run setup.exe under the program directory. -
Page 57: New Project Setup
“View, Solution Explorer”. 6. Right click on “Project80332” and select “Save Project80332”. 7. From http://developer.intel.com/design/iio/swsup/Tester1LED.htm, download the following zip file (…/Tester1LED) from the Software Support section, containing the example code files to the newly created project folder: Tester1LED.zip... -
Page 58: Configuration
® Intel IQ80332 I/O Processor Getting Started and Debugger B.3.2 Configuration Examine the main menu of Code|Lab EDE for .NET. • File • Edit Since Code|Lab is a plug-in to Visual Studio, some of these menu items are Visual Studio and some are specific to Code|Lab. -
Page 59: Flashing With Jtag
This Flash programmer only supports certain file formats: Intel Hex, Motorola srec and standard elf (executable and linking format). RedBoot.s19 and RedBoot.srec are both srec files. TBD.i32 is an ARM BootMonitor Intel Hex file. BootMonitor is an ARM version of a debug monitor, which is similar but not identical to RedBoot. -
Page 60: Using Flash Programmer
® Intel IQ80332 I/O Processor Getting Started and Debugger B.4.2 Using Flash Programmer Note: The parallel port must be set to EPP mode or the Macraigor Raven does not work properly. Download the RedBoot executable files from the following location: http://developer.intel.com/design/intelxscale/dev_tools/021022/index.htm... -
Page 61: Debugging Out Of Flash
Note: Rebuild cleans and builds. Clean deletes the old .o files in the project and build compiles, links, and produces the executable files. 3. When there are errors, carefully go back through Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Getting Started and Debugger Section B.3.2, “Configuration”. -
Page 62: Running The Code|Lab Debugger
® Intel IQ80332 I/O Processor Getting Started and Debugger Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the ATI Code|Lab Debug Reference Manual for more detailed information. -
Page 63: Displaying Source Code
5. Press “Go” again and notice that the program loop is infinite. 6. Press the “Halt” icon to stop execution. 7. Close the debugger and cycle power to the board. Evaluation Platform Board Manual ® Intel IQ80332 I/O Processor Getting Started and Debugger... -
Page 64: Stepping Through The Code
® Intel IQ80332 I/O Processor Getting Started and Debugger B.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. This exercise steps through the code and utilizes a few of the most common step tools. -
Page 65: Exploring The Code|Lab Debug Windows
Memory window. The ATU header begins at 0xffffe100 and contains a known number (8086). Also look at the base and limit registers for the memory and Flash devices, at 0xffffe508 and ffffe688 respectively, since they were initialized by RedBoot. Use the Intel Manual, to see what the values mean. -
Page 66: Registers Window
® Intel IQ80332 I/O Processor Getting Started and Debugger B.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. -
Page 67: Debugging Basics
B.9.2 Hardware and Software Breakpoints The following section provides a brief overview of breakpoints. See the Intel Developer’s Manual, for more detailed information. B.9.2.1 Software Breakpoints Software breakpoints are setup and utilized via debugger utilities (such as Code|Lab). -
Page 68: C.9.3 Exceptions/Trapping
® Intel IQ80332 I/O Processor Getting Started and Debugger B.9.3 C.9.3 Exceptions/Trapping A debug exception causes the processor to re-direct execution to a debug event handling routine. The ® Intel 80200 processor debug architecture defines the following debug exceptions: •...