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PCI
6.1
6.2
Hardware Design Guide
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PCI Controller
The PCI Controller provides a 64-bit, 66-MHz-capable PCI Local Bus Specification, Version 2.2*
®
interface to the Intel
IXP2800 or Intel
32-bit and/or 33-MHz PCI devices. The PCI controller provides the following functions:
•
Target Access (external Bus Master access to SRAM, DRAM, and CSRs)
•
Master Access (Intel XScale
•
Two DMA Channels
•
Mailbox and Doorbell Registers for Intel XScale
•
PCI Arbiter
The network processor can be configured to act as a PCI central function (for use in a stand-alone
system), where it provides the PCI reset signal, or as an add-in device, where it uses the PCI reset
signal as the chip reset input.
PCI Interface
The IXP28XX network processor has a PCI controller with its own bus arbiter supporting two
external masters in addition to the PCI unit's initiator interface. The base card implementation
requires more than two external masters; therefore, the arbiter in both the ingress and egress
INXP2800 network processor is disabled and the arbiter in the 21555 PCI-PCI bridge is enabled
instead. In this implementation, both the ingress and egress network processors provide their PCI
request signals as output to the 21555 and use the 21555's grant signals as inputs. The PCI Bus in
the IXP28XX network processor is a CMOS bus and is based on reflected wave rather than
incident wave signaling.
As shown in
Figure
63, the Primary PCI bus is connected to the cPCI back plane through the J1 and
J2 connectors. The interface is configurable to be 32-bit or 64-bit and the interface runs at the clock
speed of the cPCI backplane. The configuration master PCI-PCI bridge provides reset and
arbitration to all devices on its secondary side. The secondary bus is 3.3 V, 64-bit, and 66 MHz.
®
IXP2850 Network Processor. It is also compatible to
®
core or Microengine access to PCI target devices)
®
core to host communication
IXP28XX Network Processor
PCI
6
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