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Note: DRCG 3.3 V can come up if StopB and/or PwrdnB pins are low.
Figure 7.
3.2.6
Hardware Design Guide
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2. Power up the V
to 1.8 V and V
CCR_IO
— Both V
and V
CCR_IO
supply.
— V
should be generated through a voltage divider from V
REF
3. Power up the IXP28XX network processor to 1.35 V (V
— V
is connected to V
CCR
4. Enable the DRCG clock output.
— Apply 3.3 V after V
Figure 7
illustrates the power-up sequence.
Power-up Sequence
referred power-up sequence:
The 1.8V and 1.5V supplies can come up in any order
before or after the 2.5V, 1.3V, and 3.3V supplies
RDRAM 2.5V
VCMOS 1.8V
DRCG 3.3V can come up if StopB
and/or wrdnB pins are low
IXP28XX Network Processor Power-Up Considerations
when using NexMod* Memory Modules
The following are additional design considerations for the IXP28XX network processor's power-
up sequence when using NexMod* modules. Because each channel can have a separate power
source for V
and V
when using the HCD memory modules and V
TERM
CMOS
supply for the IXP28XX network processor, is common to all three channels as shown in
the following requirement must be satisfied by the power delivery design:
•
The system designer must ensure that V
— In most cases this can be guaranteed by the power sequence order.
to 1.8 V.
TERM
must be raised simultaneously and tied to the same 1.8 V power
TERM
through an LC filter.
CCR_A
, with StopB and PwrdnB pins high.
CCR_IO
VCCR_IO =
Vterm 1.8V
Intel
®
Network Processor
Vref 1.4V
1.3V
and V
CCR_IO
IXP28XX Network Processor
.
TERM
and V
).
CCR
CCR_A
DRCG 3.3V
(Stop / Pwrdn )
IXP2800
the RDRAM I/O
CCR_IO,
never differ by more than 1.6 V.
TERM
RDRAM
3410-02
Figure
8,
37
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