Sony VPL-X2000U Service Manual page 282

C Board Waveforms
1 2
1
0.6Vp-p (H) 0.7Vp-p (H)
TP5012 (MCLKP) TP5013 (MCLKN)
5 6
0.48Vp-p (H) 1Vp-p (H)
TP5206 (B IN) TP5201 (R BFO)
9 !º
2
6.8Vp-p (H) 5Vp-p (V)
TP5210 (1/2 CLK) TP5209 (H SYNC)
!£ !¢
7.6Vp-p (H) 7.6Vp-p (H)
TP5511 (B SID) TP5512 (R SID)
!¶ !•
10Vp-p (H)
10Vp-p (H)
TP5503 (G7)
TP5504 (B INV)
3
@¡ @™
10Vp-p (H) 10Vp-p (H)
TP5507 (R INV) TP5508 (R1)
4
5
A B
3 4
0.5Vp-p (H) 0.5Vp-p (H)
TP5202 (R IN) TP5204 (G IN)
8
7
1Vp-p (H) 1Vp-p (H)
TP5203 (G BFO) TP5205 (B BFO)
!™
!¡
5Vp-p (H) 7.6Vp-p (H)
TP5212 (V SYNC) TP5510 (G SID)
!∞ !§
10Vp-p (H) 10Vp-p (H)
TP5501 (G INV) TP5502 (G1)
!ª @º
10Vp-p (H) 10Vp-p (H)
TP5505 (G1) TP5506 (G7)
@£
10Vp-p (H)
TP5509 (R7)
C
C C
C Board IC Block Diagrams
CXA2112R-T6 (IC5501, 5502, 5301, 5302, 5304, 5305)
48 47 46
INVERT
AMP
DLY CNT 49
MCLK 50
MCLK/ 51
INV CNT 52 D
VDD 53
CLOCK
DELAY
CLK OUT 54
CLK OUT/ 55
D.P 56
D.P 57
DGND 58
S/H
PULSES
CLK IN 59
TIMING
GENERATOR
60
NC
CLK IN/ 61
PRG 62
OFFSET CANCEL
MODE TIMING
NC 63
NC 64
1 2 3 4 5 6 7 8 9 10 11 12 13
M62399FP-TE2 (IC5402)
CS0 CS1 CS2 VDD VCC A04
19 18
20 17 16 15
CHIP SELECT
8BIT
UPPER DIGITS
SEGMENT R-2R
8BIT LATCH
8BIT LATCH
8BIT
UPPER DIGITS
SEGMENT R-2R
1 2 3 8 4
R SCL SDA VREFL A05
9-66 9-66
D E
MB8814APFV-ER (IC5401)
CSO 16
CS1 17
CS2 18
MOD 19
SCL 20
45 44 43 42 41 40 39 38 37 36 35 34 33
SDA 21
SID BIAS VCOM
32 GND2
D0
SH OUT1
S/H S/H S/H BUFFER 31
8BIT
LATCH
NC 1ch
OFFSET CANCEL 30
S/H S/H S/H BUFFER 29 SH OUT2
VDD1 22
R–2R
OFFSET CANCEL NC
28 LADDER
VSS1 23
CIRCUIT
S/H S/H S/H BUFFER 27 SH OUT3
26
PVcc
OFFSET CANCEL
25 D.P
24 D.P
VCC 13
23 PGND
GND 24
NC
22
S/H S/H S/H BUFFER 21 SH OUT4
1
OFFSET CANCEL 20 NC
A01
S/H S/H S/H 19 SH OUT5
BUFFER
OFFSET CANCEL 18
NC
S/H S/H S/H 17 SH OUT6
BUFFER
TC74VHC08F (IC5404)
OFFSET CANCEL
14 15 16
VCC 4B 4A 4Y
14 13 12 11
1 2 3 4
A03 A02 A01 VREFU2
1A 1B 1Y 2A
14 13 12 11
8BIT 8BIT 8BIT
UPPER DIGITS UPPER DIGITS UPPER DIGITS
TC74VHC240F (IC5215, 5216)
SEGMENT R-2R SEGMENT R-2R SEGMENT R-2R
8BIT LATCH 8BIT LATCH 8BIT LATCH
20 19 18 17
8BIT LATCH 8BIT LATCH 8BIT LATCH
8BIT 8BIT 8BIT
UPPER DIGITS UPPER DIGITS UPPER DIGITS
SEGMENT R-2R SEGMENT R-2R SEGMENT R-2R
1 2 3 4
5 6 7 10 9
A06 A07 A08 GND VREFU1
F G
I C BUS INTERFACE 2
D/A&I/O CONTROL LOGIC
D7 D0 D7 D0 D7 D0 D7
8BIT 8BIT 8BIT
LATCH LATCH LATCH
4ch 5ch 12ch
VDD2
R–2R R–2R R–2R 15
LADDER LADDER LADDER
14 VSS2
CIRCUIT CIRCUIT CIRCUIT
8
2 3 4 5 6 7 8 9 10 11 12
A04 D7/A05 D0/A012
3B 3A 3Y
10 9 8
5 6 7
2B 2Y GND
16 15 14 13 12 11
5 6 7 8 9 10
H