Sony VPL-X2000U Service Manual page 242

MB88141APFV-ER (IC1004, 1008)
1
CSO 16
CS1 17
2
CS2 18 I C BUS INTERFACE
D/A&I/O CONTROL LOGIC
MOD 19
SCL 20
SDA 21
D0 D7 D0 D7 D0 D7 D0 D7
8BIT 8BIT 8BIT 8BIT
LATCH LATCH LATCH LATCH
1ch 4ch 5ch 12ch
VDD1 22 R–2R R–2R R–2R R–2R
LADDER LADDER LADDER LADDER
VSS1 23
CIRCUIT CIRCUIT CIRCUIT CIRCUIT
VCC 13
GND 24
2
1 2 3 4 5 6 7 8 9 10 11 12
A01 A04 D7/A05 D0/A012
MC74F244MEL (IC9104, 9105)
OEA 1 20 VCC
A1 2 19 OEB
YB4 3 18 YA1
A2 4 17 B4
5 16 YA2
YB3
A3 6 15 B3
3
YB2 7 14 YA3
A4 8 13 B2
YB1 9 12 YA4
GND 10 11 B1
MC74HC4538AF-T2 (IC1409)
VDD 2-C 2-CR 2-RD 2-CK 2-CR 2-Q 2-Q
16 15 14 13 12 11 10 9
4
1 2 3 4 5 6 7 8
1-C 1-CR 1-RD 1-CK 1-CK 1-Q 1-Q GND
MM1112XFBE (IC1403, 1404)
1 8
SW
2 6dB 7 OUT
SW
5
IN2 VCC
3 6
15K 15K
NC 4 5 NC
BIAS
A B
NJM2235M-T1 (IC1102)
V OUT V+ VIN3
8 7 6 5
BUFFER
BIAS
1 2 3 4
CTL1 VIN2 CTL2
15 VDD2
14
VSS2
NJM2240M (IC1103)
8
PHASE DIVIDER
FSC OUT 1 8 NC
COMPARATOR CIRCUIT
SEARCH
DET FIL 2 7 R
CIRCUIT
GND 3 6 +V
4 VCO 5 OSC C
OSC OUT
NJM2533M (IC1105, 1106)
GND V OUT V NC
8 7 6 5
BIAS
1 2 3 4
V IN1 SW1 V IN2 NC
PC74HC123D-T (IC1909, 9005)
A 1 16
B 2 15
RD 3 14
RD
Q Q
Q 4 13
D Q Q
Q 5 12
RD
C 6 11
R 7 10
GND 8 9
SN74HCU04ANS-E20 (IC1251)
VCC
14 13 12 11 10 9 8
1 2 3 4 5 6 7
GND
C
BA BA
SN75157 (IC1903)
NON INV IN1 1 8 V
CC
OUT1 2 7 INV IN2
OUT2 3 6 NON INV IN2
GND 4
5 INV IN2
TDA4665T-T (IC1401)
DIGITAL
SUPPLY
VP2
1
N.C 2
SIGNAL
CLAMPING
DGND 3
pre-amplifiers
GND 4
SIGNAL
CLAMPING
PULSE IN 5
NC 6
FREQUENCY
SANDCASTLE
PHASE
DETECTOR
DETECTOR
IC 7
GND 8
TDA9141-N2C (IC1402)
32 31 30 29 28
SDA SCL
VERTICAL
I2C OUS
SYNCSEP
I/O
PROT
LCA
O PROT
SYNCSEP
CHROMA
ACC
SWITCH
DELAY TRAP
VDD
R
C
Q
Q
1 2 3 4 5
RD
B
A
TLC2932IPW-E20 (IC9001)
LOGIC VCO
VDD SELECT OUT FIN-A FIN-B
1 2 3 4 5
1/2 DIVIDER
VCO
14 13 12 11 10
VCO R BIAS VCO VCO VCO
VDD IN GND INHIBIT
9-26 9-26
D E
TLC2933IPW-E20 (IC9004)
LOGIC V 1
DD
TEST 2
VCO OUT 3
FIN-A 4
FIN-B 5
PFD OUT 6
LOGIC GND 7
TLC5733AIPM (IC9006)
+ (R-Y)IN
16
–
15 NC
SAMPLE
LINE
AND-
LP
MEMORY + (B-Y)IN
14
HOLD –
addition output V (A) 63
IN
stages buffers V (A) 61
RT
NC
13
V (A)
RB 1
SAMPLE
+ (B-Y)OUT
LINE 12 CLPV(A) 60
–
AND- LP
MEMORY
1 (A)
HOLD BLAS 59
V CC (A) 62
+ GND(A) 64
11 (R-Y)OUT
3MHz shifting clock –
OE(A) 2
DIVIDER
BY 192
10 A GND
V (B)
IN 50
DIVIDER
6MHz
LP V RT (B) 52
CCO BY 2
ANALOG
9 VP1 V RB (B)
SUPPLY 48
CLPV(B)
53
1 BLAS (B)
54
V (B)
CC 51
GND(B)
49
OE(B)
47
V IN (C) 31
V RT (C) 29
V RB (C)
27 26 25 24 23 22 21 20 19 18 17 33
CLPV(C)
28
1 BLAS (C)
27
V CC (C) 30
GND(C)
32
U
YA
OE(C)
TIMING V 34
HA MATRIX SWITCH
GENERATOR W
CLP EXTCLP 55
CLPEN 57
NT/PAL 3
HORIZONTAL IDENT
SIM
PLL SYSTEM
R-Y
SECAM FILTER SECAM
SWITCH B-Y
CLOCHE TUNING DEMOD
CHROMA CHROMA PAL/NTSC
MUE
BANDPASS PLL DEMOD
BIAS
FSC
BUFFER
FSC
uPC659AGS-E2 (IC1253)
6 7 8 9 10 11 12 13 14 15 16 VRT 1
NC 2
AVCC 3
VIN 4
AGND
5
PCL 6
VCL 7
PFD LOGIC
AVCC 8
OUT GND
6 7
AGND 9
VRB 10
AVCC 11
AGND 12
PFD
9 8
PFD NC
INHIBIT
F
14 VCO V
DD
13 RBIAS
RING BIAS
12 CONT VOL
OSC CONTROL
11 VCO GND
CHARGE
PFD
10 VCO INH
PUMP
9 PFD INH
8 NC
V DD DGND
26 25
CLK A
6
8
8 8
I V(A)1-8
SAMPLING
13
COMPARATOR
8
14 V DD (QA)
DATA
5 DGND(QA)
LATCH
CLAMP
CONTROL
CLK B
17
8 8 8
I D(B)1-8
MUX
SAMPLING 24
8
COMPARATOR WITH
16 V (QB)
OUTPUT FORMAT DD
DATA
15 DGND(QB)
LATCH
CLAMP
CONTROL
CLK C
36
8 8 8
I D(C)1-8
SAMPLING
43
8
COMPARATOR
35 V (QC)
DD
DATA
44 DGND(QC)
LATCH
CLAMP
CONTROL
CLK A
CLAMP PULSE OUTPUT FORMAT 46 MODE0
CLK B CLOCK
INT/EXT /TEST 45 MODE1
CLK A GENERATOR
CONTROL SWITCHING
4
TEST
56 58
CLK XSYNC
TIMING
24 CLK
GENERATOR
CLAMP S/H
23 OVER
22 DB1(MSB)
21
D/A DB2
20 DB3
5
19 DGND
18 DVCC
17
5 5 DB4
16 DB5
15 DB6
FLASH
14 DB7
3
A/D CONV.
13 DB8(LSB)
G H