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4.2
Alphabetical Signals Reference
Table 4-3.
Signal Description (Sheet 1 of 10)
Name
A[35:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
BNR#
64
Type
A[35:3]# (Address) define a 2
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
Input/
are source synchronous signals and are latched into the receiving
Output
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1-MB boundary. Assertion of A20M# is only supported
Input
in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All bus
Input/
agents observe the ADS# activation to begin protocol checking,
Output
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as shown
below.
Input/
Signals
Output
REQ[4:0]#, A[16:3]#
A[35:17]#
The differential pair BCLK (Bus Clock) determines the FSB frequency.
All processor FSB agents must receive these signals to drive their
outputs and latch their inputs.
Input
All external timing parameters are specified with respect to the rising
edge of BCLK0 crossing V
BNR# (Block Next Request) is used to assert a bus stall by any bus
Input/
agent unable to accept new bus transactions. During a bus stall, the
Output
current bus owner cannot issue any new transactions.
Land Listing and Signal Descriptions
Description
36
-byte physical memory address
Section 6.1
for more details.
Associated
Strobe
ADSTB0#
ADSTB1#
.
CROSS
Datasheet
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