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3.
V
IL
low value.
4.
V
IH
high value.
5.
V
IH
comply with the signal quality specifications in
6.
The V
7.
I
OL
8.
Leakage to V
9.
Leakage to V
2.8.3.1
Platform Environment Control Interface (PECI) DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors, chipsets, and external thermal monitoring devices. The
Yorkfield processor contains Digital Thermal Sensors (DTS) distributed throughout die.
These sensors are implemented as analog-to-digital converters calibrated at the factory
for reasonable accuracy to provide a digital representation of relative processor
temperature. PECI provides an interface to relay the highest DTS temperature within a
die to external management devices for thermal/fan speed control. More detailed
information may be found in the Platform Environment Control Interface (PECI)
Specification.
Table 2-12. PECI DC Electrical Limits
Symbol
V
in
V
hysteresis
V
n
V
p
I
source
I
sink
I
leak+
I
leak-
C
bus
V
noise
NOTES:
1. V
supplies the PECI interface. PECI behavior does not affect V
TT
refer to
2. The leakage specification applies to powered devices on the PECI bus.
3. The input buffers use a Schmitt-triggered input design for improved noise immunity.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
.
2.8.3.2
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See
termination. Refer to the appropriate platform design guidelines for specific
implementation details.
26
is defined as the voltage range at a receiving agent that will be interpreted as a logical
is defined as the voltage range at a receiving agent that will be interpreted as a logical
and V
may experience excursions above V
OH
referred to in these specifications refers to instantaneous V
TT
is measured at 0.10 * V
TT.
with land held at V
SS
with land held at 300 mV.
TT
Definition and Conditions
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V
= 0.75 * V
)
OH
TT
Low level output sink
(V
= 0.25 * V
)
OL
TT
High impedance state leakage to V
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above 300 MHz
Table 2-3
for VTT specifications.
Table 2-7
for details on which GTL+ signals do not include on-die
. However, input signal drivers must
TT
Chapter
3.
I
is measured at 0.90 * V
OH
.
TT
Min
-0.15
0.1 * V
TT
0.275 * V
TT
0.550 * V
TT
-6.0
0.5
N/A
TT
N/A
-
0.1 * V
TT
Electrical Specifications
.
TT
TT.
Max
Units
Notes
V
V
TT
-
V
0.500 * V
V
TT
0.725 * V
V
TT
N/A
mA
1.0
mA
50
µA
10
µA
10
pF
-
V
p-p
min/max specifications. Please
TT
Datasheet
1
2
3
2
4
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