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2.7.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in
measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are <
10 ns in duration may be ignored. These measurements of processor die level
overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or
equal to 100 MHz bandwidth limit.
2.8
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as V
separate power planes for each processor (and chipset), separate V
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families. Design guidelines for the processor front
side bus are detailed in the appropriate platform design guides (refer to
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see
platform design guidelines for details. Termination resistors (R
provided on the processor silicon and are terminated to V
provide on-die termination, thus eliminating the need to terminate the bus on the
motherboard for most GTL+ signals.
2.8.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[3:0] as a reference level. In
this document, the term "GTL+ Input" refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle.
and asynchronous.
22
Table 2-13
for GTLREF specifications). Refer to the applicable
Table 2-6
identifies which signals are common clock, source synchronous,
Electrical Specifications
Table 2-5
when
. Because platforms implement
TT
and V
CC
TT
Section
) for GTL+ signals are
TT
. Intel chipsets will also
TT
supplies
1.2).
Datasheet
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