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Electrical Specifications
Table 2-6.
FSB Signal Groups
Signal Group
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
GTL+ Source
Synchronous I/O
GTL+ Strobes
CMOS
Open Drain
Output
Open Drain
Input/Output
FSB Clock
Power/Other
NOTES:
1.
Refer to
2.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See
4.
PROCHOT# signal type is open drain output and CMOS input.
Datasheet
Type
Synchronous to
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
BCLK[1:0]
Synchronous to
ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0#
BCLK[1:0]
DRDY#, HIT#, HITM#, LOCK#
Synchronous to
assoc. strobe
Synchronous to
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
BCLK[1:0]
A20M#,
INTR, LINT1/NMI, SMI#
TCK, TDI, TDI_M, TMS, TRST#, BSEL[2:0], VID[7:0],
PSI#
FERR#/PBE#, IERR#, THERMTRIP#, TDO, TDO_M
PROCHOT#
Clock
BCLK[1:0], ITP_CLK[1:0]
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[3:0], COMP[8,3:0], RESERVED,
TESTHI[13,11:10,7:0], VCC_SENSE,
VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0]
Section 4.2
for signal descriptions.
Signals
Signals
3
REQ[4:0]#, A[16:3]#
3
A[35:17]#
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DPSLP#, DPRSTP#,
3
, STPCLK#, PWRGOOD, SLP#,
4
2
Section 6.1
for details.
1
3
, DBSY#,
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
IGNNE#, INIT#, LINT0/
2
, VTT_OUT_LEFT,
23
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