Clock Specifications; Front Side Bus Clock (Bclk[1:0]) And Processor Clocking; Core Frequency To Fsb Multiplier Configuration - Intel Quad-Core Xeon 3300 Series Datasheet

2.9

Clock Specifications

2.9.1

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor's core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. The processor supports Half Ratios between 7.5
and 13.5, refer to
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative.
Table 2-14. Core Frequency to FSB Multiplier Configuration
Multiplication of
System Core
Frequency to FSB
Frequency
NOTES:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
2.9.2 FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]).
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
28
Table 2-14 for the processor supported ratios.
Core Frequency
(333 MHz BCLK/1333
1/6
1/7
1/7.5
1/8
1/8.5
1/9
1/9.5
1/10
1/10.5
1/11
1/11.5
1/12
1/12.5
1/13
1/13.5
1/14
1/15
Table 2-15 defines the possible combinations of the signals and the
Notes
MHz FSB)
2 GHz
2.33 GHz
2.50 GHz
2.66 GHz
2.83 GHz
3 GHz
3.16 GHz
3.33 GHz
3.50 GHz
3.66 GHz
3.83 GHz
4 GHz
4.16 GHz
4.33 GHz
4.50 GHz
4.66 GHz
5 GHz
Electrical Specifications
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