Differential Clock Waveform; Measurement Points For Differential Clock Waveforms - Intel Quad-Core Xeon 3300 Series Datasheet

Electrical Specifications
7. Duty Cycle (High time/Period) must be between 40 and 60%
.
Figure 2-3.

Differential Clock Waveform

Threshold
Region
Figure 2-4.

Measurement Points for Differential Clock Waveforms

+150 mV
0.0V
-150 mV
Diff
Datasheet
Tph
BCLK1
V )
CROSS (ABS
BCLK0
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
Slew_rise
T5 = BCLK[1:0] rise and fall time through the swing region
§
Ringback
V )
Margin
CROSS (ABS
Tpl
Slew _fall
V_swing
Overshoot
VH
Rising Edge
Ringback
Falling Edge
Ringback
VL
Undershoot
+150mV
0.0V
-150mV
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