Bclk[1:0] Specifications; Front Side Bus Differential Bclk Specifications; Fsb Differential Clock Specifications (1333 Mhz Fsb) - Intel Quad-Core Xeon 3300 Series Datasheet

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2.9.4

BCLK[1:0] Specifications

Table 2-16. Front Side Bus Differential BCLK Specifications
Symbol
V
Input Low Voltage
L
V
Input High Voltage
H
Absolute Crossing
V
Point
CROSS(abs)
Range of Crossing
∆V
Points
CROSS
V
Overshoot
OS
V
Undershoot
US
Differential Output
V
Swing
SWING
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
3.
"Steady state" voltage, not including overshoot or undershoot.
4.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
5.
Measurement taken from differential waveform.
Table 2-17. FSB Differential Clock Specifications (1333 MHz FSB)
BCLK[1:0] Frequency
T1: BCLK[1:0] Period
T2: BCLK[1:0] Period Stability
T5: BCLK[1:0] Rise and Fall Slew
Rate
Slew Rate Matching
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor core
frequencies based on a 333 MHz BCLK[1:0].
2.
The period specified here is the average period. A given period may vary from this
specification as governed by the period stability specification (T2). Min period specification
is based on -300 PPM deviation from a 3 ns period. Max period specification is based on
the summation of +300 PPM deviation from a 3 ns period and a +0.5% maximum variance
due to spread spectrum clocking.
3.
For the clock jitter specification, refer to the CK505 Clock Synthesizer Specification.
4.
In this context, period stability is defined as the worst case timing difference between
successive crossover voltages. In other words, the largest absolute difference between
adjacent clock periods must be less than the period stability.
5.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Measurement taken from differential waveform.
6.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is
measured using a ±75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations.
30
Parameter
-0.300
T# Parameter
Min
Typ
Max
-0.30
N/A
N/A
N/A
N/A
1.15
0.300
N/A
0.550
N/A
N/A
0.140
N/A
N/A
1.4
N/A
N/A
0.300
N/A
N/A
Min
Nom
Max
331.633
-
333.367
2.99970
-
3.01538
-
-
150
2.5
-
8
N/A
N/A
20
Electrical Specifications
1
Unit
Figure
Notes
V
2-3
3
V
2-3
3
V
2-3
2
V
2-3
-
V
2-3
4
V
2-3
4
V
2-4
5
1
Unit
Figure
Notes
MHz
-
7
ns
2-3
2
ps
2-3
3, 4
V/ns
2-4
5
%
-
6
Datasheet

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