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Table 25.
Signal Description (Sheet 1 of 9)
Name
TESTHI[13:0]
THERMDA
THERMDC
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCA
VCCIOPLL
VCC_SENSE
VCC_MB_
REGULATION
72
Type
TESTHI[13:0] must be connected to the processor's appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal
Input
description) through a resistor for proper processor operation. See
Section 2.4
for more details.
Other
Thermal Diode Anode. See
Other
Thermal Diode Cathode. See
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a
temperature approximately 20 °C above the maximum T
Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a level beyond where permanent
silicon damage may occur. Upon assertion of THERMTRIP#, the
processor will shut off its internal clocks (thus, halting program
execution) in an attempt to reduce the processor junction
temperature. To protect the processor, its core voltage (V
be removed following the assertion of THERMTRIP#. Driving of the
Output
THERMTRIP# signal is enabled within 10 µs of the assertion of
PWRGOOD (provided VTTPWRGD, V
disabled on de-assertion of PWRGOOD (if VTTPWRGD, V
are not valid, THERMTRIP# may also be disabled). Once activated,
THERMTRIP# remains latched until PWRGOOD, VTTPWRGD, V
V
is de-asserted. While the de-assertion of the PWRGOOD,
CC
VTTPWRGD, VTT or VCC signal will de-assert THERMTRIP#, if the
processor's junction temperature remains at or above the trip level,
THERMTRIP# will again be asserted within 10 µs of the assertion of
PWRGOOD (provided VTTPWRGD, V
TMS (Test Mode Select) is a JTAG specification support signal used
Input
by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is
Input
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
Input
must be driven low during power on Reset.
VCC are the power lands for the processor. The voltage supplied to
Input
these lands is determined by the VID[5:0] pins.
Input
VCCA provides isolated power for the internal processor core PLLs.
Input
VCCIOPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE is an isolated low impedance connection to processor
Output
core power (V
). It can be used to sense or measure voltage near
CC
the silicon with little noise.
This land is provided as a voltage regulator feedback sense point
for V
. It is connected internally in the processor package to the
CC
Output
sense point land U27 as described in the Voltage Regulator-Down
(VRD) 10.1 Design Guide for Desktop Socket 775.
Land Listing and Signal Descriptions
Description
Section
5.2.7.
Section
5.2.7.
, and V
are asserted) and is
TT
CC
, and V
are asserted).
TT
CC
.
C
) must
CC
, or V
TT
CC
or
TT
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