Fsb Frequency Select Signals (Bsel[2:0]); Phase Lock Loop (Pll) And Filter; Bsel[2:0] Frequency Table For Bclk[1:0] - Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet

2.7.2

FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]).
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The Pentium 4 processor will operate at an 800 MHz FSB frequency (selected by a
200 MHz BCLK[1:0] frequency).
For more information about these signals, refer to
Table 18.

BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2
L
L
L
L
H
H
H
H
2.7.3

Phase Lock Loop (PLL) and Filter

V and V
CCA
Pentium 4 processor silicon. Since these PLLs are analog, they require low noise power
supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O
timings as well as internal core timings (i.e., maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from V
The AC low-pass requirements, with input at V
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in
30
Table 18 defines the possible combinations of the signals and the
BSEL1 BSEL0
L
L
H
H
H
H
L
L
are power sources required by the PLL clock generators for the
CCIOPLL
Section
FSB Frequency
L RESERVED
H RESERVED
H RESERVED
L 200 MHz
L RESERVED
H RESERVED
H RESERVED
L RESERVED
are as follows:
TT
Figure 3.
Electrical Specifications
4.2.
.
TT
Datasheet