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Table 25.
Signal Description (Sheet 1 of 9)
Name
BR0#
BSEL[2:0]
COMP[5:4,1:0]
D[63:0]#
66
Type
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
Input/
signal is sampled to determine the agent ID = 0.
Output
This signal does not have on-die termination and must be
terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to
select the processor input clock frequency.
possible combinations of the signals and the frequency associated
with each combination. The required frequency is determined by
Output
the processor, chipset and clock synthesizer. All agents must
operate at the same frequency. For more information about these
signals, including termination recommendations, refer to
Chapter
2.
COMP[1:0] must be terminated to V
Analog
precision resistors. COMP[5:4] must be terminated to V
system board using precision resistors.
D[63:0]# (Data) are the data signals. These signals provide a 64-
bit data path between the processor FSB agents, and must connect
the appropriate pins/lands on all such agents. The data driver
asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of
16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DBI#.
Quad-Pumped Signal Groups
Input/
Output
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
Land Listing and Signal Descriptions
Description
Table 18
on the system board using
SS
DSTBN#/
DBI#
DSTBP#
0
0
1
1
2
2
3
3
defines the
on the
TT
Datasheet
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