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AGP Port Design Guidelines
8.2.8.
AGP VDDQ and VCC
AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics
controller and VDDQ is the interface voltage.
8.2.9.
VREF Generation for AGP 2.0 (2X and 4X)
8.2.9.1.
1.5-V AGP Interface (2X/4X)
The voltage divider networks consist of AC and DC elements. The reference voltage that should be
supplied to the Vref pins of the GMCH/MCH and the graphics controller is ½ * VDDQ. Two, 1-k ±
1% resistors can be used to divide VDDQ down to the necessary voltage level.
The Vref divider network should be placed as close to the AGP interface as is practical to get the benefit
of the common mode power supply effects. However, the trace spacing around the Vref signals must be
a minimum of 25 mils to reduce crosstalk and maintain signal integrity.
8.2.10.
AGP Compensation
The 852GME chipset MCH-M AGP interface supports resistive buffer compensation. For PCBs with
characteristic impedance of 55 , tie the GRCOMP pin to a 40.2
via a 10-mil wide, very short ( 0.5 inches) trace.
AGP Link:
http://www.intel.com/technology/agp/info.htm
AGP StressTool Link:
http://www.intel.com/technology/agp/downloads/agp_stress.htm
8.2.11.
PM_SUS_CLK/AGP_PIPE# Design Consideration
The following design consideration provides the option to support both AGP and DVO devices with one
ADD Connector. Refer to Figure 49 and customer reference schematics for more detail.
The GMCH expects either the PM_SUS_CLK signal from the ADD connector when there is a no AGP
device or the AGP_PIPE# signal when there is an AGP device. The AGP_TYPEDET# signal is driven
high when no AGP card is detected, allowing DPMS_CLK to be driven by PM_SUS_CLK. In the case
where an AGP card is detected, AGP_TYPE# signal goes high which allows DMPS_CLK to be driven
by AGP_PIPE#.
138
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®
Intel
852GME, Intel
852GMV and Intel
± 1% pull-down resistor (to ground)
®
852PM Chipset Platforms Design Guide
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