Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet page 61

Pentium 4 processor 6x1 sequence, on 65 nm process in the 775-land lga package supporting hyper-threading technology and 64 arhitecture
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Land Listing and Signal Descriptions
Table 24.Numerical Land Assignment
Land
Land Name
#
H28
H29
H3
H30
H4
H5
TESTHI10
H6
H7
H8
H9
J1
VTT_OUT_LEFT
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J2
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J3
J30
J4
J5
J6
J7
J8
J9
Datasheet
Signal Buffer
Type
VSS
Power/Other
FC15
Power/Other
VSS
Power/Other
BSEL1
Power/Other
RSP#
Common Clock
Power/Other
VSS
Power/Other
VSS
Power/Other
VSS
Power/Other
VSS
Power/Other
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
DP0#
Common Clock Input/Output
DP3#
Common Clock Input/Output
VCC
Power/Other
VCC
Power/Other
COMP4
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
VCC
Power/Other
FC22
Power/Other
VCC
Power/Other
VSS
Power/Other
REQ1#
Source Synch Input/Output
REQ4#
Source Synch Input/Output
VSS
Power/Other
VCC
Power/Other
VCC
Power/Other
Table 24.Numerical Land Assignment
Land
Direction
Land Name
#
K1
LINT0
Output
K2
VSS
K23
VCC
Output
K24
VCC
Input
K25
VCC
Input
K26
VCC
K27
VCC
K28
VCC
K29
VCC
K3
A20M#
Output
K30
VCC
K4
REQ0#
K5
VSS
K6
REQ3#
K7
VSS
K8
VCC
L1
LINT1
L2
TESTHI13
L23
VSS
L24
VSS
L25
VSS
Input
L26
VSS
L27
VSS
L28
VSS
L29
VSS
L3
VSS
L30
VSS
L4
A06#
L5
A03#
L6
VSS
L7
VSS
L8
VCC
Output
M1
VSS
M2
THERMTRIP#
M23
VCC
M24
VCC
M25
VCC
M26
VCC
M27
VCC
M28
VCC
Signal Buffer
Direction
Type
Asynch GTL+
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch GTL+
Input
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Asynch GTL+
Input
Asynch GTL+
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Asynch GTL+
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
61

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