Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet page 46

Pentium 4 processor 6x1 sequence, on 65 nm process in the 775-land lga package supporting hyper-threading technology and 64 arhitecture
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Table 23.Alphabetical Land
Land Name
FC18
FC20
FC9
FERR#/PBE#
GTLREF0
GTLREF1
HIT#
HITM#
IERR#
IGNNE#
IMPSEL
INIT#
ITP_CLK0
ITP_CLK1
LINT0
LINT1
LL_ID0
LL_ID1
LOCK#
MCERR#
MSID0
MSID1
PROCHOT#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
46
Assignments
Land
Signal Buffer
#
Type
AE3
Power/Other
E5
Power/Other
D23
Power/Other
R3
Asynch GTL+
H1
Power/Other
H2
Power/Other
D4
Common Clock Input/Output
E4
Common Clock Input/Output
AB2
Asynch GTL+
N2
Asynch GTL+
F6
Power/Other
P3
Asynch GTL+
AK3
TAP
AJ3
TAP
K1
Asynch GTL+
L1
Asynch GTL+
V2
Power/Other
AA2
Power/Other
C3
Common Clock Input/Output
AB3 Common Clock Input/Output
W1
Power/Other
V1
Power/Other
AL2
Asynch GTL+ Input/Output
N1
Power/Other
K4
Source Synch Input/Output
J5
Source Synch Input/Output
M6
Source Synch Input/Output
K6
Source Synch Input/Output
J6
Source Synch Input/Output
A20
AC4
AE4
AE6
AH2
C9
D1
D14
D16
E23
Land Listing and Signal Descriptions
Table 23.Alphabetical Land
Assignments
Direction
Land Name
Output
RESERVED
Output
RESERVED
Output
RESERVED
Output
RESERVED
Input
RESERVED
Input
RESERVED
RESERVED
RESERVED
Output
RESERVED
Input
RESET#
Input
RS0#
Input
RS1#
Input
RS2#
Input
RSP#
Input
SKTOCC#
Input
SMI#
Output
STPCLK#
Output
TCK
TDI
TDO
Output
TESTHI0
Output
TESTHI1
TESTHI10
Input
TESTHI11
TESTHI12
TESTHI13
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
THERMDA
THERMDC
THERMTRIP#
TMS
TRDY#
Land
Signal Buffer
Direction
#
Type
E6
E7
F23
F29
G10
G6
N4
N5
P5
G23 Common Clock
Input
B3
Common Clock
Input
F5
Common Clock
Input
A3
Common Clock
Input
H4
Common Clock
Input
AE8
Power/Other
Output
P2
Asynch GTL+
Input
M3
Asynch GTL+
Input
AE1
TAP
Input
AD1
TAP
Input
AF1
TAP
Output
F26
Power/Other
Input
W3
Power/Other
Input
H5
Power/Other
Input
P1
Power/Other
Input
W2
Power/Other
Input
L2
Asynch GTL+
Input
F25
Power/Other
Input
G25
Power/Other
Input
G27
Power/Other
Input
G26
Power/Other
Input
G24
Power/Other
Input
F24
Power/Other
Input
G3
Power/Other
Input
G4
Power/Other
Input
AL1
Power/Other
AK1
Power/Other
M2
Asynch GTL+
Output
AC1
TAP
Input
E3
Common Clock
Input
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