Pwrgood And Tap Signal Group Dc Specifications - Intel HH80552PG0962M - Pentium 4 3.4 GHz Processor Datasheet

Pentium 4 processor 6x1 sequence, on 65 nm process in the 775-land lga package supporting hyper-threading technology and 64 arhitecture
Hide thumbs Also See for HH80552PG0962M - Pentium 4 3.4 GHz Processor:
Table of Contents

Advertisement

Table 11.
GTL+ Asynchronous Signal Group DC Specifications
Symbol
Input Leakage
I
LI
Current
Output Leakage
I
LO
Current
R
Buffer On Resistance
ON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
IL
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals,
V
= GTLREF + (0.10 * V
IH
4. V
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
IH
5. V
and V
may experience excursions above V
IH
OH
specifications.
6. The V
referred to in these specifications refers to instantaneous V
TT
7. All outputs are open drain.
8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
9. Leakage to V
SS
10.Leakage to V
TT
.
Table 12.

PWRGOOD and TAP Signal Group DC Specifications

Symbol
V
Input Hysteresis
HYS
PWRGOOD Input low-
to-high threshold
voltage
V
T+
TAP Input low-to-high
threshold voltage
PWRGOOD Input high-
to-low threshold
voltage
V
T-
TAP Input high-to-low
threshold voltage
V
Output High Voltage
OH
I
Output Low Current
OL
I
Input Leakage Current
LI
I
Output Leakage Current
LO
R
Buffer On Resistance
ON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
V
represents the amount of hysteresis, nominally centered about 0.5 * V
3.
HYS
4. The V
referred to in these specifications refers to instantaneous V
TT
5. 0.24 V is defined at 20% of nominal V
6. The TAP signal group must meet the signal quality specifications.
7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
8. Leakage to Vss with land held at V
9. Leakage to V
TT
26
Parameter
) and V
= GTLREF – (0.10 * V
TT
IL
with land held at V
.
TT
with land held at 300 mV.
Parameter
0.5 * (V
0.5 * (V
0.5 * (V
of 1.2 V.
TT
.
TT
with land held at 300 mV.
Min
N/A
± 200
N/A
± 200
6
).
TT
. However, input signal drivers must comply with the signal quality
TT
.
TT
Min
120
V
0.5 * (V
TT +
HYS_MIN
+ 0.24)
V
)
0.5 * (V
TT +
HYS_MIN
0.4 * V
0.6 * V
TT
– V
)
0.5 * (V
TT
HYS_MAX
N/A
6
.
TT
Electrical Specifications
Max
Unit
µA
µA
12
W
Max
Unit
Notes
396
mV
V
TT +
HYS_MAX
V
+ 0.24)
V
)
V
TT +
HYS_MAX
V
TT
– V
)
V
TT
HYS_MIN
V
V
TT
22.2
mA
± 200
µA
± 200
µA
12
W
, for all TAP inputs.
TT
Datasheet
1
Notes
9
10
1, 2
3
4, 5
4
4
4
4, 6
7
8
9

Advertisement

Table of Contents
loading

This manual is also suitable for:

Pentium 4 631Pentium 4 641Pentium 4 651Pentium 4 661

Table of Contents