Decoupling Guidelines; Vcc Core Decoupling; Phase Lock Loop (Pll) Decoupling - Intel 810A3 Design Manual

System Design Considerations
7.2

Decoupling Guidelines

7.2.1 Vcc
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Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep an interconnect resistance from the regulator (or VRM pins) to the Socket pins of less
than 0.3m ohm. This can be accomplished by keeping a maximum distance of 1.0 inches between
the regulator output and Socket Vcc pins. The recommended Vcc
wide (the width of the VRM 8.2 connector) by 1.0 inch long (maximum distance between the 370-
pin socket and the VRM connector) plane segment with a standard 1-ounce plating. Bulk
decoupling for the large current swings when the part is powering on, or entering/exiting low
power states, is provided on the voltage regulation module (VRM) defined in the VRM 8.2 DC-DC
Converter Design Guidelines. The Vcc
recommended minimum dI
Adequate decoupling capacitance should be placed near the power pins of the Intel
processor PPGA. In order to obtain optimal performance Intel recommends using 10 or more
4.7 uF 1206-style capacitors and 19 or more 1.0 uF 0805-style capacitors when using a
conventional Voltage Regulator Module. Inductance should be reduced by connecting capacitors
directly to the Vcc
vias to the plane. Be sure to include the effects of board inductance within the simulation. Also,
when choosing the capacitors to use, keep in mind the operating temperatures that will be seen and
the rated tolerance.
Bulk capacitance with a low Effective Series Resistance (ESR) should also be placed near the
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Intel Celeron™ processor PPGA to handle changes in average current between the low-power
and normal operating states. About 9000 uF of capacitance with an ESR of 5m ohm makes a good
starting point for simulations, although more capacitance may be needed to bring the ESR down to
this level due to the current technology in the industry. Voltage Regulator Modules already contain
this bulk capacitance. Be sure to determine what is available on the market before choosing
parameters for the models. Also, include power supply response time and cable inductance in a full
simulation.
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The Intel
the processor package. High frequency decoupling and bulk decoupling should be provided for by
the system motherboard for proper AGTL+ bus operation.
Although the system bus receives power external to the processor, this power supply will also
require the same diligent decoupling methodologies as the processor. Note that the existence of
external power entering through the I/O buffers causes Vss current to be higher than the Vcc
current. For more information the following documents are recommended:
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Intel
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Intel
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Intel
7.2.2

Phase Lock Loop (PLL) Decoupling

Isolated analog decoupling is required for the internal PLL. This should be a 22 µF ±20% capacitor
and a 22 µH ±30% inductor. The capacitor should be across the PLL1 and PLL2 pins of the
processor. The inductor should be connected from PLL1 to Vcc
7-6
Decoupling
/dt while maintaining the required tolerances.
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and Vss planes with minimal trace length between the component pads and
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Celeron™ processor PPGA does not contain high frequency decoupling capacitance on
Pentium III Processor AGTL+ Guidelines
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Pentium III Processor Power Distribution Guideline
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Pentium III Processor Developer's Manual
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supply should be capable of delivering a
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Intel
interconnect is a 2.0 inch
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Celeron™
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810A3 Chipset Design Guide
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