Processor May Cache Prefetched Data From Remapped Memory Region - AMD 3200 - Athlon 64 2.0 GHz Processor Manual

Revision Guide for AMD Family h Models h- Fh Processors Rev October
Processor May Cache Prefetched Data from Remapped
Memory Region
Description
Prefetches from a write back WB DRAM memory region may persist when that memory region is remapped to
an uncacheable UC or write combining WC memory type
Potential Effect on System
Data could be cached in a modified state from the remapped memory region which will not be probed however
this can only occur if a prefetch operation persists through the invalidation or flushing of TLB entries and cache
lines before the remapped memory region is accessible in a coherent manner There have been no observations
of this erratum on silicon
Suggested Workaround
None recommended Optionally system software may set MSRC b DC CFG DisHwPf
during system boot if frequent run-time remapping of memory types as described is expected
Fix Planned
Yes
Product Errata