AMD 3200 - Athlon 64 2.0 GHz Processor Manual page 74

Revision Guide for AMD Family
Processor May Check DRAM Address Maps While Using
L Cache as General Storage during Boot
Description
BIOS accesses while running with L cache as general storage may hit in the L cache while they are
concurrently checked against the DRAM Base and Limit Registers in the northbridge In the event that this
check is performed while the DRAM address maps are not yet completed by BIOS the northbridge may flag a
protocol error if it cannot find a DRAM address map associated with the BIOS access AMD has only observed
this issue when node-interleaving is enabled DRAM Base Limit Register IntlvEn D F x
b
Potential Effect on System
The processor may recognize a northbridge machine check exception for a link protocol error The machine
check exception may cause a sync flood and or a system reset This may be observed as a system hang
The machine check has the following signature
The MC STAT register MSR
miscellaneous valid of MC STAT may or may not be set
Bits of the MC ADDR register MSR
packet was issued to a non-coherent link
The conditions under which this erratum may be observed as a system failure are sensitive to the core and
northbridge frequencies AMD has only observed this erratum with one G
software P-state core frequency is less than the northbridge frequency
Suggested Workaround
BIOS should set MSRC
should restore MSRC
Fix Planned
No fix planned
h Models h- Fh Processors
is equal to BA
A to b prior to using L cache as general storage during boot and then
A to it's original value after completing L cache as general storage
Product Errata
B C F Bit
is equal to b indicating that a coherent-only
processor configuration where the
Rev October
C C
error overflow or bit