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Registers
4.9
Interrupt Mask Set Register (IMSR)
The interrupt mask set register (IMSR) enables the DDR2 memory controller interrupt. The IMSR is shown
in
Figure 27
and described in
Note:
If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask clear
register (IMCR), the interrupt is not enabled and neither bit is set to 1.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
Value
31-3
Reserved
0
2
LTMSET
0
1
1-0
Reserved
0
48
DDR2 Memory Controller
Table
29.
Figure 27. Interrupt Mask Set Register (IMSR)
Reserved
R-0
Table 29. Interrupt Mask Set Register (IMSR) Field Descriptions
Description
Reserved
Line trap interrupt set. Write a 1 to set LTMSET and the LTMCLR bit in the interrupt mask clear register
(IMCR); a write of 0 has no effect.
Line trap interrupt is not enabled; a write of 1 to the LTMCLR bit in IMCR occurred.
Line trap interrupt is enabled.
Reserved
Reserved
R-0
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16
3
2
1
0
LTMSET
Reserved
R/W-0
R-0
SPRUEQ4C – February 2009
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