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TMS320C6747 DSP
Texas Instruments TMS320C6747 DSP Manuals
Manuals and User Guides for Texas Instruments TMS320C6747 DSP. We have
3
Texas Instruments TMS320C6747 DSP manuals available for free PDF download: Reference Manual, Manual, User Manual
Texas Instruments TMS320C6747 DSP Reference Manual (1472 pages)
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 8.08 MB
Table of Contents
Table of Contents
2
Purpose of the Peripheral
16
29.1.3 Functional Block Diagram
17
29.2.2 Signal Descriptions
17
29.2.9 DMA Event Support
17
Preface
64
Introduction
66
2 DSP Subsystem
68
Tms320C674X Megamodule Block Diagram
69
Introduction
69
DSP Interrupt Map
70
Tms320C674X Megamodule
70
Memory Map
74
Advanced Event Triggering (AET)
75
System Interconnect
76
TMS320C6745/C6747 DSP System Interconnect Matrix
77
Introduction
77
System Interconnect Block Diagram
78
4 System Memory
79
Introduction
80
Peripherals
81
5 Memory Protection Unit (MPU)
82
MPU Block Diagram
83
Introduction
83
MPU Memory Regions
84
MPU Default Configuration
84
Device Master Settings
85
Memory Protection Ranges
85
Permission Fields
86
Request Type Access Controls
86
Permission Structures
86
Protection Check
87
MPU_BOOTCFG_ERR Interrupt Sources
88
Invalid Accesses and Exceptions
88
Memory Protection Unit 1 (MPU1) Registers
89
Memory Protection Unit 2 (MPU2) Registers
89
MPU Registers
89
Revision ID Register (REVID)
91
Configuration Register (CONFIG)
91
Revision ID Register (REVID) Field Descriptions
91
Configuration Register (CONFIG) Field Descriptions
91
Interrupt Raw Status/Set Register (IRAWSTAT)
92
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
92
Interrupt Enable Status/Clear Register (IENSTAT)
93
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
93
Interrupt Enable Set Register (IENSET)
94
Interrupt Enable Clear Register (IENCLR)
94
Interrupt Enable Set Register (IENSET) Field Descriptions
94
Interrupt Enable Clear Register (IENCLR) Field Descriptions
94
Fixed Range End Address Register (FXD_MPEAR)
95
Fixed Range Start Address Register (FXD_MPSAR)
95
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)
96
Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions
96
Programmable Range N Start Address Registers (Progn_Mpsar)
97
MPU1 Programmable Range N Start Address Register (Progn_Mpsar)
97
MPU2 Programmable Range N Start Address Register (Progn_Mpsar)
97
MPU1 Programmable Range N Start Address Register (Progn_Mpsar) Field Descriptions
97
MPU2 Programmable Range N Start Address Register (Progn_Mpsar) Field Descriptions
97
Programmable Range N End Address Registers (Progn_Mpear)
98
MPU1 Programmable Range N End Address Register (Progn_Mpear)
98
MPU2 Programmable Range N End Address Register (Progn_Mpear)
98
MPU1 Programmable Range N End Address Register (Progn_Mpear) Field Descriptions
98
MPU2 Programmable Range N End Address Register (Progn_Mpear) Field Descriptions
98
Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
99
Programmable Range Memory Protection Page Attributes Register (Progn_Mppa)
99
Programmable Range Memory Protection Page Attributes Register (Progn_Mppa) Field Descriptions
99
Fault Address Register (FLTADDRR)
100
Fault Address Register (FLTADDRR) Field Descriptions
100
Fault Status Register (FLTSTAT)
101
Fault Status Register (FLTSTAT) Field Descriptions
101
Fault Clear Register (FLTCLR)
102
Fault Clear Register (FLTCLR) Field Descriptions
102
6 Device Clocking
103
Overview
104
Device Clock Inputs
104
System Clock Domains
104
Frequency Flexibility
105
Overall Clocking Diagram
105
Example PLL Frequencies
106
Peripheral Clocking
107
6.3.1 USB Clocking
107
USB Clocking Diagram
107
USB Clock Multiplexing Options
108
6.3.2 EMIFB Clocking
109
EMIFB Clocking Diagram
110
EMIFB MCLK Frequencies
110
6.3.3 EMIFA Clocking
111
EMIFA Clocking Diagram
111
EMIFA Frequencies
111
6.3.4 EMAC Clocking
112
EMAC Clocking Diagram
112
EMAC Reference Clock Frequencies
113
6.3.5 I/O Domains
114
Peripherals
114
7 Phase-Locked Loop Controller (PLLC)
115
Introduction
116
PLL0 Control
116
PLL0 Structure
117
7.2.1 Device Clock Generation
118
System PLLC0 Output Clocks
118
7.2.2 Steps for Changing PLL0 Domain Frequency
119
Locking/Unlocking PLL Register Access
120
PLLC Registers
121
PLL Controller (PLLC) Registers
121
Revision Identification Register (REVID)
122
Reset Type Status Register (RSTYPE)
122
Revision Identification Register (REVID) Field Descriptions
122
Reset Type Status Register (RSTYPE) Field Descriptions
122
PLL Control Register (PLLCTL)
123
PLL Control Register (PLLCTL) Field Descriptions
123
OBSCLK Select Register (OCSEL)
124
OBSCLK Select Register (OCSEL) Field Descriptions
124
PLL Multiplier Control Register (PLLM)
125
PLL Pre-Divider Control Register (PREDIV)
125
PLL Multiplier Control Register (PLLM) Field Descriptions
125
PLL Pre-Divider Control Register (PREDIV) Field Descriptions
125
PLL Controller Divider 1 Register (PLLDIV1)
126
PLL Controller Divider 2 Register (PLLDIV2)
126
PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions
126
PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions
126
PLL Controller Divider 3 Register (PLLDIV3)
127
PLL Controller Divider 4 Register (PLLDIV4)
127
PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions
127
PLL Controller Divider 4 Register (PLLDIV4) Field Descriptions
127
PLL Controller Divider 5 Register (PLLDIV5)
128
PLL Controller Divider 6 Register (PLLDIV6)
128
PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions
128
PLL Controller Divider 6 Register (PLLDIV6) Field Descriptions
128
PLL Controller Divider 7 Register (PLLDIV7)
129
PLL Controller Divider 7 Register (PLLDIV7) Field Descriptions
129
Oscillator Divider 1 Register (OSCDIV)
130
Oscillator Divider 1 Register (OSCDIV) Field Descriptions
130
PLL Post-Divider Control Register (POSTDIV)
131
PLL Controller Command Register (PLLCMD)
131
PLL Post-Divider Control Register (POSTDIV) Field Descriptions
131
PLL Controller Command Register (PLLCMD) Field Descriptions
131
PLL Controller Status Register (PLLSTAT)
132
PLL Controller Status Register (PLLSTAT) Field Descriptions
132
PLL Controller Clock Align Control Register (ALNCTL)
133
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
133
PLLDIV Ratio Change Status Register (DCHANGE)
134
PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions
134
Clock Enable Control Register (CKEN)
135
Clock Enable Control Register (CKEN) Field Descriptions
135
Clock Status Register (CKSTAT)
136
Clock Status Register (CKSTAT) Field Descriptions
136
SYSCLK Status Register (SYSTAT)
137
SYSCLK Status Register (SYSTAT) Field Descriptions
137
Emulation Performance Counter 0 Register (EMUCNT0)
138
Emulation Performance Counter 1 Register (EMUCNT1)
138
Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions
138
Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions
138
8 Power and Sleep Controller (PSC)
139
Introduction
140
Power Domain and Module Topology
140
PSC0 Default Module Configuration
140
PSC1 Default Module Configuration
141
8.2.1 Power Domain States
142
8.2.2 Module States
142
SPRUH91D - March 2013 - Revised September 2016
142
Module States
143
Executing State Transitions
144
8.3.1 Power Domain State Transitions
144
8.3.2 Module State Transitions
144
Icepick Emulation Support in the PSC
145
PSC Interrupts
145
8.5.1 Interrupt Events
145
Icepick Emulation Commands
145
PSC Interrupt Events
145
8.5.2 Interrupt Registers
146
8.5.3 Interrupt Handling
147
PSC Registers
148
Power and Sleep Controller 0 (PSC0) Registers
148
Power and Sleep Controller 1 (PSC1) Registers
148
Revision Identification Register (REVID)
149
Interrupt Evaluation Register (INTEVAL)
149
Revision Identification Register (REVID) Field Descriptions
149
Interrupt Evaluation Register (INTEVAL) Field Descriptions
149
PSC0 Module Error Pending Register 0 (Modules 0-15) (MERRPR0)
150
PSC1 Module Error Pending Register 0 (Modules 0-31) (MERRPR0)
150
PSC0 Module Error Pending Register 0 (MERRPR0)
150
PSC1 Module Error Pending Register 0 (MERRPR0)
150
PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions
150
PSC0 Module Error Clear Register 0 (Modules 0-15) (MERRCR0)
151
PSC1 Module Error Clear Register 0 (Modules 0-31) (MERRCR0)
151
PSC0 Module Error Clear Register 0 (MERRCR0)
151
PSC1 Module Error Clear Register 0 (MERRCR0)
151
PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions
151
Power Error Pending Register (PERRPR)
152
Power Error Clear Register (PERRCR)
152
Power Error Pending Register (PERRPR) Field Descriptions
152
Power Error Clear Register (PERRCR) Field Descriptions
152
Power Domain Transition Command Register (PTCMD)
153
Power Domain Transition Command Register (PTCMD) Field Descriptions
153
Power Domain Transition Status Register (PTSTAT)
154
Power Domain Transition Status Register (PTSTAT) Field Descriptions
154
Power Domain 0 Status Register (PDSTAT0)
155
Power Domain 0 Status Register (PDSTAT0) Field Descriptions
155
Power Domain 1 Status Register (PDSTAT1)
156
Power Domain 1 Status Register (PDSTAT1) Field Descriptions
156
Power Domain 0 Control Register (PDCTL0)
157
Power Domain 0 Control Register (PDCTL0) Field Descriptions
157
Power Domain 1 Control Register (PDCTL1)
158
Power Domain 1 Control Register (PDCTL1) Field Descriptions
158
Power Domain 0 Configuration Register (PDCFG0)
159
Power Domain 0 Configuration Register (PDCFG0) Field Descriptions
159
Power Domain 1 Configuration Register (PDCFG1)
160
Power Domain 1 Configuration Register (PDCFG1) Field Descriptions
160
Module Status N Register (Mdstatn)
161
Module Status N Register (Mdstatn) Field Descriptions
161
PSC0 Module Control N Register (Modules 0-15) (Mdctln)
162
PSC0 Module Control N Register (Mdctln)
162
PSC0 Module Control N Register (Mdctln) Field Descriptions
162
PSC1 Module Control N Register (Modules 0-31) (Mdctln)
163
PSC1 Module Control N Register (Mdctln)
163
PSC1 Module Control N Register (Mdctln) Field Descriptions
163
9 Power Management
164
Introduction
165
Power Consumption Overview
165
PSC and PLLC Overview
165
Features
166
Power Management Features
166
Clock Management
167
9.5.1 Module Clock ON/OFF
167
9.5.2 Module Clock Frequency Scaling
167
9.5.3 PLL Bypass and Power down
167
DSP Sleep Mode Management
168
9.6.1 C674X DSP CPU Sleep Mode
168
9.6.2 C674X Megamodule Sleep Mode
168
RTC-Only Mode
168
Additional Peripheral Power Management Considerations
169
9.8.1 USB PHY Power down Control
169
9.8.2 EMIFB Memory Clock Gating
169
10 System Configuration (SYSCFG) Module
170
10.1 Introduction
171
10.2 Protection
172
System Configuration (SYSCFG) Module Register Access
172
10.2.1 Requirements to Access SYSCFG Registers
173
10.3 Master Priority Control
174
Master Ids
174
10.4 Interrupt Support
175
10.4.1 Interrupt Events and Requests
175
10.4.2 Interrupt Multiplexing
175
10.4.3 Host-DSP Communication Interrupts
175
Default Master Priority
175
10.5 SYSCFG Registers
176
System Configuration Module (SYSCFG) Registers
176
Revision Identification Register (REVID)
177
Device Identification Register 0 (DEVIDR0)
177
Revision Identification Register (REVID) Field Descriptions
177
Device Identification Register 0 (DEVIDR0) Field Descriptions
177
Boot Configuration Register (BOOTCFG)
178
Silicon Revision Identification Register (CHIPREVID)
178
Boot Configuration Register (BOOTCFG) Field Descriptions
178
Silicon Revision Identification Register (CHIPREVID) Field Descriptions
178
Kick Registers (KICK0R-KICK1R)
179
Kick 0 Register (KICK0R)
179
Kick 1 Register (KICK1R)
179
Kick 0 Register (KICK0R) Field Descriptions
179
Kick 1 Register (KICK1R) Field Descriptions
179
Host 1 Configuration Register (HOST1CFG)
180
Host 1 Configuration Register (HOST1CFG) Field Descriptions
180
10.5.7 Interrupt Registers
181
Interrupt Raw Status/Set Register (IRAWSTAT)
181
Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions
181
Interrupt Enable Status/Clear Register (IENSTAT)
182
Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions
182
Interrupt Enable Register (IENSET)
183
Interrupt Enable Clear Register (IENCLR)
183
Interrupt Enable Register (IENSET) Field Descriptions
183
Interrupt Enable Clear Register (IENCLR) Field Descriptions
183
10.5.8 Fault Registers
184
End of Interrupt Register (EOI)
184
Fault Address Register (FLTADDRR)
184
End of Interrupt Register (EOI) Field Descriptions
184
Fault Address Register (FLTADDRR) Field Descriptions
184
Fault Status Register (FLTSTAT)
185
Fault Status Register (FLTSTAT) Field Descriptions
185
Master Priority Registers (MSTPRI0-MSTPRI2)
186
Master Priority 0 Register (MSTPRI0)
186
Master Priority 0 Register (MSTPRI0) Field Descriptions
186
Master Priority 1 Register (MSTPRI1)
187
Master Priority 1 Register (MSTPRI1) Field Descriptions
187
Master Priority 2 Register (MSTPRI2)
188
Master Priority 2 Register (MSTPRI2) Field Descriptions
188
Pin Multiplexing Control Registers (PINMUX0-PINMUX19)
189
Pin Multiplexing Control 0 Register (PINMUX0)
189
Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions
189
Pin Multiplexing Control 1 Register (PINMUX1)
191
Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions
191
Pin Multiplexing Control 2 Register (PINMUX2)
193
Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions
193
Pin Multiplexing Control 3 Register (PINMUX3)
195
Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions
195
Pin Multiplexing Control 4 Register (PINMUX4)
196
Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions
196
Pin Multiplexing Control 5 Register (PINMUX5)
197
Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions
197
Pin Multiplexing Control 6 Register (PINMUX6)
199
Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions
199
Pin Multiplexing Control 7 Register (PINMUX7)
201
Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions
201
Pin Multiplexing Control 8 Register (PINMUX8)
203
Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions
203
Pin Multiplexing Control 9 Register (PINMUX9)
205
Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions
205
Pin Multiplexing Control 10 Register (PINMUX10)
207
Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions
207
Pin Multiplexing Control 11 Register (PINMUX11)
209
Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions
209
Pin Multiplexing Control 12 Register (PINMUX12)
211
Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions
211
Pin Multiplexing Control 13 Register (PINMUX13)
213
Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions
213
Pin Multiplexing Control 14 Register (PINMUX14)
215
Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions
215
Pin Multiplexing Control 15 Register (PINMUX15)
217
Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions
217
Pin Multiplexing Control 16 Register (PINMUX16)
219
Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions
219
Pin Multiplexing Control 17 Register (PINMUX17)
221
Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions
221
Pin Multiplexing Control 18 Register (PINMUX18)
223
Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions
223
Pin Multiplexing Control 19 Register (PINMUX19)
225
Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions
225
Suspend Source Register (SUSPSRC)
226
Suspend Source Register (SUSPSRC) Field Descriptions
226
Chip Signal Register (CHIPSIG)
228
Chip Signal Register (CHIPSIG) Field Descriptions
228
Chip Signal Clear Register (CHIPSIG_CLR)
229
Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions
229
Chip Configuration 0 Register (CFGCHIP0)
230
Chip Configuration 0 Register (CFGCHIP0) Field Descriptions
230
Chip Configuration 1 Register (CFGCHIP1)
231
Chip Configuration 1 Register (CFGCHIP1) Field Descriptions
232
Chip Configuration 2 Register (CFGCHIP2)
235
Chip Configuration 2 Register (CFGCHIP2) Field Descriptions
235
Chip Configuration 3 Register (CFGCHIP3)
237
Chip Configuration 3 Register (CFGCHIP3) Field Descriptions
237
Chip Configuration 4 Register (CFGCHIP4)
238
Chip Configuration 4 Register (CFGCHIP4) Field Descriptions
238
11 Boot Considerations
239
11.1 Introduction
240
12 Programmable Real-Time Unit Subsystem (PRUSS)
241
13 Enhanced Capture (Ecap) Module
243
13.1 Introduction
244
13.1.1 Purpose of the Peripheral
244
13.1.2 Features
244
13.2 Architecture
245
Multiple Ecap Modules
245
13.2.1 Capture and APWM Operating Mode
246
Capture and APWM Modes of Operation
246
13.2.2 Capture Mode Description
247
Capture Function Diagram
247
Event Prescale Control
248
Prescale Function Waveforms
248
Continuous/One-Shot Block Diagram
249
Counter and Synchronization Block Diagram
250
Interrupts in Ecap Module
252
PWM Waveform Details of APWM Mode Operation
253
13.3 Applications
254
Absolute Time-Stamp Operation Rising Edge Trigger Example
255
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
255
ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
256
13.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
257
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
257
ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
258
13.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
259
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
259
ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
260
13.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
261
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
261
ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
262
Application of the APWM Mode
263
PWM Waveform Details of APWM Mode Operation
263
ECAP Initialization for APWM Mode
264
Multichannel PWM Example Using 4 Ecap Modules
265
ECAP1 Initialization for Multichannel PWM Generation with Synchronization
266
ECAP2 Initialization for Multichannel PWM Generation with Synchronization
266
ECAP3 Initialization for Multichannel PWM Generation with Synchronization
266
ECAP4 Initialization for Multichannel PWM Generation with Synchronization
266
Multiphase (Channel) Interleaved PWM Example Using 3 Ecap Modules
268
ECAP1 Initialization for Multichannel PWM Generation with Phase Control
269
ECAP2 Initialization for Multichannel PWM Generation with Phase Control
269
ECAP3 Initialization for Multichannel PWM Generation with Phase Control
269
Registers
270
Time-Stamp Counter Register (TSCTR)
270
Control and Status Register Set
270
Time-Stamp Counter Register (TSCTR) Field Descriptions
270
Counter Phase Control Register (CTRPHS)
271
Capture 1 Register (CAP1)
271
Counter Phase Control Register (CTRPHS) Field Descriptions
271
Capture 1 Register (CAP1) Field Descriptions
271
Capture 2 Register (CAP2)
272
Capture 3 Register (CAP3)
272
Capture 2 Register (CAP2) Field Descriptions
272
Capture 3 Register (CAP3) Field Descriptions
272
Capture 4 Register (CAP4)
273
ECAP Control Register 1 (ECCTL1)
273
Capture 4 Register (CAP4) Field Descriptions
273
ECAP Control Register 1 (ECCTL1) Field Descriptions
273
ECAP Control Register 2 (ECCTL2)
275
ECAP Control Register 2 (ECCTL2) Field Descriptions
275
ECAP Interrupt Enable Register (ECEINT)
276
ECAP Interrupt Enable Register (ECEINT)
277
ECAP Interrupt Enable Register (ECEINT) Field Descriptions
277
ECAP Interrupt Flag Register (ECFLG)
278
ECAP Interrupt Flag Register (ECFLG) Field Descriptions
278
ECAP Interrupt Clear Register (ECCLR)
279
ECAP Interrupt Clear Register (ECCLR) Field Descriptions
279
ECAP Interrupt Forcing Register (ECFRC)
280
ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
280
Revision ID Register (REVID)
281
Revision ID Register (REVID) Field Descriptions
281
14 Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
282
Introduction
283
14.1.2 Submodule Overview
283
Multiple Epwm Modules
284
Submodules and Signal Connections for an Epwm Module
285
Epwm Submodules and Critical Internal Signal Interconnects
286
14.1.3 Register Mapping
287
Epwm Module Control and Status Registers Grouped by Submodule
287
14.2 Architecture
288
14.2.1 Overview
288
Submodule Configuration Parameters
288
14.2.2 Proper Interrupt Initialization Procedure
291
14.2.3 Time-Base (TB) Submodule
292
Time-Base Submodule Block Diagram
292
Time-Base Submodule Signals and Registers
293
Time-Base Submodule Registers
293
Key Time-Base Signals
294
Time-Base Frequency and Period
295
Time-Base Counter Synchronization Scheme 1
296
Time-Base Up-Count Mode Waveforms
298
Time-Base Down-Count Mode Waveforms
299
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event
299
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event
300
14.2.4 Counter-Compare (CC) Submodule
301
Counter-Compare Submodule
301
Counter-Compare Submodule Signals and Registers
301
Counter-Compare Submodule Registers
302
Counter-Compare Submodule Key Signals
302
Counter-Compare Event Waveforms in Up-Count Mode
304
Counter-Compare Events in Down-Count Mode
304
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event
305
Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event
305
14.2.5 Action-Qualifier (AQ) Submodule
306
Action-Qualifier Submodule
306
Action-Qualifier Submodule Registers
306
Action-Qualifier Submodule Inputs and Outputs
307
Action-Qualifier Submodule Possible Input Events
307
Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
308
Action-Qualifier Event Priority for Up-Down-Count Mode
309
Action-Qualifier Event Priority for Up-Count Mode
309
Action-Qualifier Event Priority for Down-Count Mode
309
Behavior if CMPA/CMPB Is Greater than the Period
310
Up-Down-Count Mode Symmetrical Waveform
311
Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High
312
Epwmx Initialization for
313
Epwmx Run Time Changes for
313
Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low
314
Epwmx Initialization for
315
Epwmx Run Time Changes for
315
Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa
316
Epwmx Initialization for
317
Epwmx Run Time Changes for
317
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low
318
Epwmx Initialization for
319
Epwmx Run Time Changes for
319
Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Complementary
320
Epwmx Initialization for
321
Epwmx Run Time Changes for
321
Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low
322
Epwmx Initialization for
323
Epwmx Run Time Changes for
323
14.2.6 Dead-Band Generator (DB) Submodule
324
Dead-Band Generator Submodule
324
Dead-Band Generator Submodule Registers
324
Configuration Options for the Dead-Band Generator Submodule
325
Classical Dead-Band Operating Modes
326
Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
327
14.2.7 PWM-Chopper (PC) Submodule
328
PWM-Chopper Submodule
328
PWM-Chopper Submodule Registers
328
PWM-Chopper Submodule Signals and Registers
329
Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
330
PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
330
PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses
331
14.2.8 Trip-Zone (TZ) Submodule
332
Trip-Zone Submodule
332
Trip-Zone Submodule Registers
333
Possible Actions on a Trip Event
334
Trip-Zone Submodule Mode Control Logic
335
Trip-Zone Submodule Interrupt Logic
335
14.2.9 Event-Trigger (ET) Submodule
336
Event-Trigger Submodule
336
Event-Trigger Submodule Registers
336
Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
337
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
337
Event-Trigger Interrupt Generator
339
14.2.10 High-Resolution PWM (HRPWM) Submodule
340
HRPWM System Interface
340
Resolution Calculations for Conventionally Generated PWM
341
Resolution for PWM and HRPWM
341
Operating Logic Using MEP
342
HRPWM Submodule Registers
342
Relationship between MEP Steps, PWM Frequency and Resolution
343
Required PWM Waveform for a Requested Duty
344
CMPA Vs Duty (Left), and [CMPA:CMPAHR] Vs Duty (Right)
344
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
346
High % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
346
14.3 Applications to Power Topologies
347
14.3.1 Overview of Multiple Modules
347
Simplified Epwm Module
347
14.3.2 Key Configuration Capabilities
348
EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
348
14.3.3 Controlling Multiple Buck Converters with Independent Frequencies
349
Control of Four Buck Stages
349
Pwm1 Pwm2 Pwm3 Pwm4
349
Pwm1 ≠ F Pwm2 ≠ F Pwm3 ≠ F
349
Buck Waveforms for (Note: Only Three Bucks Shown Here)
350
Buck Waveforms for
350
EPWM1 Initialization for
351
EPWM2 Initialization for
351
EPWM3 Initialization for
351
14.3.4 Controlling Multiple Buck Converters with same Frequencies
352
Control of Four Buck Stages
352
Pwm1 )
352
Pwm2 Pwm1
353
EPWM1 Initialization for
354
EPWM2 Initialization for
354
14.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
355
Pwm2 = N × F
355
Pwm1 )
355
Pwm2 Pwm1
356
EPWM1 Initialization for
357
EPWM2 Initialization for
357
Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
358
Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
358
3-Phase Inverter Waveforms for (Only One Inverter Shown)
359
EPWM1 Initialization for
360
EPWM2 Initialization for
360
EPWM3 Initialization for
361
14.3.7 Practical Applications Using Phase Control between PWM Modules
362
Configuring Two PWM Modules for Phase Control
362
14.3.8 Controlling a 3-Phase Interleaved DC/DC Converter
363
Timing Waveforms Associated with Phase Control between 2 Modules
363
Control of a 3-Phase Interleaved DC/DC Converter
364
3-Phase Interleaved DC/DC Converter Waveforms for
365
EPWM1 Initialization for
366
EPWM2 Initialization for
366
EPWM3 Initialization for
367
14.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
368
Pwm2 Pwm1
368
ZVS Full-H Bridge Waveforms
369
EPWM1 Initialization for
370
EPWM2 Initialization for
370
14.4 Registers
371
14.4.1 Time-Base Submodule Registers
371
Time-Base Control Register (TBCTL)
371
Submodule Registers
371
Time-Base Control Register (TBCTL) Field Descriptions
372
Time-Base Status Register (TBSTS)
373
Time-Base Status Register (TBSTS) Field Descriptions
373
Time-Base Phase Register (TBPHS)
374
Time-Base Counter Register (TBCNT)
374
Time-Base Phase Register (TBPHS) Field Descriptions
374
Time-Base Counter Register (TBCNT) Field Descriptions
374
14.4.2 Counter-Compare Submodule Registers
375
Time-Base Period Register (TBPRD)
375
Time-Base Period Register (TBPRD) Field Descriptions
375
Counter-Compare Control Register (CMPCTL)
376
Counter-Compare Control Register (CMPCTL) Field Descriptions
376
Counter-Compare a Register (CMPA)
377
Counter-Compare a Register (CMPA) Field Descriptions
377
14.4.3 Action-Qualifier Submodule Registers
378
Counter-Compare B Register (CMPB)
378
Counter-Compare B Register (CMPB) Field Descriptions
378
Action-Qualifier Output a Control Register (AQCTLA)
379
Action-Qualifier Output a Control Register (AQCTLA) Field Descriptions
379
Action-Qualifier Output B Control Register (AQCTLB)
380
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
380
Action-Qualifier Software Force Register (AQSFRC)
381
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
381
14.4.4 Dead-Band Generator Submodule Registers
382
Action-Qualifier Continuous Software Force Register (AQCSFRC)
382
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
382
Dead-Band Generator Control Register (DBCTL)
383
Dead-Band Generator Control Register (DBCTL) Field Descriptions
383
Dead-Band Generator Rising Edge Delay Register (DBRED)
384
Dead-Band Generator Falling Edge Delay Register (DBFED)
384
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
384
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
384
14.4.5 PWM-Chopper Submodule Register
385
PWM-Chopper Control Register (PCCTL)
385
PWM-Chopper Control Register (PCCTL) Bit Descriptions
385
14.4.6 Trip-Zone Submodule Registers
386
Trip-Zone Select Register (TZSEL)
386
Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
386
Trip-Zone Control Register (TZCTL)
387
Trip-Zone Enable Interrupt Register (TZEINT)
387
Trip-Zone Control Register (TZCTL) Field Descriptions
387
Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
387
Trip-Zone Flag Register (TZFLG)
388
Trip-Zone Flag Register (TZFLG) Field Descriptions
388
Trip-Zone Clear Register (TZCLR)
389
Trip-Zone Force Register (TZFRC)
389
Trip-Zone Clear Register (TZCLR) Field Descriptions
389
Trip-Zone Force Register (TZFRC) Field Descriptions
389
14.4.7 Event-Trigger Submodule Registers
390
Event-Trigger Selection Register (ETSEL)
390
Event-Trigger Selection Register (ETSEL) Field Descriptions
390
Event-Trigger Prescale Register (ETPS)
391
Event-Trigger Prescale Register (ETPS) Field Descriptions
391
Event-Trigger Flag Register (ETFLG)
392
Event-Trigger Clear Register (ETCLR)
392
Event-Trigger Flag Register (ETFLG) Field Descriptions
392
Event-Trigger Clear Register (ETCLR) Field Descriptions
392
14.4.8 High-Resolution PWM Submodule Registers
393
Event-Trigger Force Register (ETFRC)
393
Event-Trigger Force Register (ETFRC) Field Descriptions
393
Time-Base Phase High-Resolution Register (TBPHSHR)
394
Counter-Compare a High-Resolution Register (CMPAHR)
394
Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions
394
Counter-Compare a High-Resolution Register (CMPAHR) Field Descriptions
394
HRPWM Configuration Register (HRCNFG)
395
HRPWM Configuration Register (HRCNFG) Field Descriptions
395
15 Enhanced Quadrature Encoder Pulse (Eqep) Module
396
15.1 Introduction
397
Optical Encoder Disk
397
QEP Encoder Output Signal for Forward/Reverse Movement
398
Index Pulse Example
398
15.2 Architecture
400
15.2.1 EQEP Inputs
400
15.2.2 Functional Description
400
Functional Block Diagram of the Eqep Peripheral
401
Quadrature Decoder Unit (QDU)
402
Functional Block Diagram of Decoder Unit
402
Quadrature Decoder Truth Table
403
Quadrature Decoder State Machine
404
Quadrature-Clock and Direction Decoding
404
Position Counter and Control Unit (PCCU)
405
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)
406
Position Counter Underflow/Overflow (QPOSMAX = 4)
407
Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)
409
Strobe Event Latch (QEPCTL[SEL] = 1)
410
Eqep Position-Compare Unit
411
Eqep Position-Compare Event Generation Points
412
Eqep Position-Compare Sync Output Pulse Stretcher
412
15.2.5 Eqep Edge Capture Unit
413
Eqep Edge Capture Unit
414
Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
414
Eqep Edge Capture Unit - Timing Details
415
15.2.6 Eqep Watchdog
416
Eqep Watchdog Timer
416
15.2.7 Unit Timer Base
417
15.2.8 Eqep Interrupt Structure
417
Eqep Unit Time Base
417
EQEP Interrupt Generation
417
15.3 Eqep Registers
418
Eqep Position Counter Register (QPOSCNT)
419
Eqep Position Counter Initialization Register (QPOSINIT)
419
Eqep Maximum Position Count Register (QPOSMAX)
419
Eqep Position Counter Register (QPOSCNT) Field Descriptions
419
Eqep Position Counter Initialization Register (QPOSINIT) Field Descriptions
419
Eqep Maximum Position Count Register (QPOSMAX) Field Descriptions
419
Eqep Position-Compare Register (QPOSCMP)
420
Eqep Index Position Latch Register (QPOSILAT)
420
Eqep Strobe Position Latch Register (QPOSSLAT)
420
Eqep Position-Compare Register (QPOSCMP) Field Descriptions
420
Eqep Index Position Latch Register (QPOSILAT) Field Descriptions
420
Eqep Strobe Position Latch Register (QPOSSLAT) Field Descriptions
420
Eqep Position Counter Latch Register (QPOSLAT)
421
Eqep Unit Timer Register (QUTMR)
421
Eqep Unit Period Register (QUPRD)
421
Eqep Position Counter Latch Register (QPOSLAT) Field Descriptions
421
Eqep Unit Timer Register (QUTMR) Field Descriptions
421
Eqep Unit Period Register (QUPRD) Field Descriptions
421
Eqep Watchdog Timer Register (QWDTMR)
422
Eqep Watchdog Period Register (QWDPRD)
422
Eqep Watchdog Timer Register (QWDTMR) Field Descriptions
422
Eqep Watchdog Period Register (QWDPRD) Field Description
422
QEP Decoder Control Register (QDECCTL)
423
Eqep Control Register (QEPCTL)
423
Eqep Decoder Control Register (QDECCTL) Field Descriptions
423
Eqep Control Register (QEPCTL)
424
Eqep Control Register (QEPCTL) Field Descriptions
424
Eqep Capture Control Register (QCAPCTL)
426
Eqep Capture Control Register (QCAPCTL) Field Descriptions
426
Eqep Position-Compare Control Register (QPOSCTL)
427
Eqep Position-Compare Control Register (QPOSCTL) Field Descriptions
427
Eqep Interrupt Enable Register (QEINT)
428
Eqep Interrupt Enable Register (QEINT) Field Descriptions
428
Eqep Interrupt Flag Register (QFLG)
429
Eqep Interrupt Flag Register (QFLG) Field Descriptions
429
Eqep Interrupt Clear Register (QCLR)
430
Eqep Interrupt Clear Register (QCLR) Field Descriptions
430
Eqep Interrupt Force Register (QFRC)
432
Eqep Interrupt Force Register (QFRC) Field Descriptions
432
Eqep Status Register (QEPSTS)
433
Eqep Status Register (QEPSTS) Field Descriptions
433
Eqep Capture Timer Register (QCTMR)
434
Eqep Capture Period Register (QCPRD)
434
Eqep Capture Timer Latch Register (QCTMRLAT)
434
Eqep Capture Time Register (QCTMR) Field Descriptions
434
Eqep Capture Period Register (QCPRD) Field Descriptions
434
Eqep Capture Timer Latch Register (QCTMRLAT) Field Descriptions
434
Eqep Capture Period Latch Register (QCPRDLAT)
435
Eqep Revision ID Register (REVID)
435
Eqep Capture Period Latch Register (QCPRDLAT) Field Descriptions
435
Eqep Revision ID Register (REVID) Field Descriptions
435
SPRUH91D - March 2013 - Revised September 2016
436
16 Enhanced Direct Memory Access (EDMA3) Controller
436
16.1 Introduction
437
16.1.1 Overview
437
16.1.2 Features
437
16.1.3 Functional Block Diagram
439
16.1.4 Terminology Used in this Document
439
EDMA3 Controller Block Diagram
439
16.2 Architecture
441
16.2.1 Functional Overview
441
EDMA3 Channel Controller (EDMA3CC) Block Diagram
442
EDMA3 Transfer Controller (EDMA3TC) Block Diagram
443
16.2.2 Types of EDMA3 Transfers
444
Definition of ACNT, BCNT, and CCNT
444
A-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
445
AB-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
446
Parameter RAM (Param)
447
Param Set
447
EDMA3 Channel Parameter Description
448
Dummy and Null Transfer Request
451
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy Param Set)
452
Linked Transfer Example
455
Link-To-Self Transfer Example
456
16.2.4 Initiating a DMA Transfer
457
16.2.5 Completion of a DMA Transfer
460
Expected Number of Transfers for Non-Null Transfer
460
16.2.6 Event, Channel, and Param Mapping
461
EDMA3 DMA Channel to Param Mapping
462
QDMA Channel to Param Mapping
463
16.2.7 EDMA3 Channel Controller Regions
464
Shadow Region Registers
464
Shadow Region Registers
465
16.2.8 Chaining EDMA3 Channels
466
16.2.9 EDMA3 Interrupts
466
Chain Event Triggers
466
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
467
Number of Interrupts
468
Interrupt Diagram
469
Error Interrupt Operation
472
Event Queue(S)
473
EDMA3 Transfer Controller (EDMA3TC)
475
16.2.12 Event Dataflow
478
16.2.13 EDMA3 Prioritization
479
16.2.14 EDMA3CC and EDMA3TC Performance and System Considerations
481
Read/Write Command Optimization Rules
481
EDMA3 Operating Frequency (Clock Control)
482
16.2.16 Reset Considerations
482
16.2.17 Power Management
482
16.2.18 Emulation Considerations
483
16.3 Transfer Examples
483
16.3.1 Block Move Example
483
Block Move Example Param Configuration
484
16.3.2 Subframe Extraction Example
485
Subframe Extraction Example Param Configuration
485
16.3.3 Data Sorting Example
486
Data Sorting Example Param Configuration
487
16.3.4 Peripheral Servicing Example
488
Servicing Incoming Mcbsp Data Example
488
Servicing Incoming Mcbsp Data Example Param
489
Servicing Peripheral Burst Example
490
Servicing Peripheral Burst Example Param
490
Servicing Continuous Mcbsp Data Example
491
Servicing Continuous Mcbsp Data Example Param
492
Servicing Continuous Mcbsp Data Example Reload Param
492
Ping-Pong Buffering for Mcbsp Data Example
495
Ping-Pong Buffering for Mcbsp Example Param
496
Ping-Pong Buffering for Mcbsp Example Pong Param
496
Ping-Pong Buffering for Mcbsp Example Ping Param
497
Intermediate Transfer Completion Chaining Example
499
Single Large Block Transfer Example
499
16.4 Registers
500
16.4.1 Parameter RAM (Param) Entries
500
Smaller Packet Data Transfers Example
500
EDMA3 Channel Controller (EDMA3CC) Parameter RAM (Param) Entries
500
Channel Options Parameter (OPT)
501
Channel Options Parameters (OPT) Field Descriptions
501
Channel Source Address Parameter (SRC)
503
A Count/B Count Parameter (A_B_CNT)
503
Channel Source Address Parameter (SRC) Field Descriptions
503
A Count/B Count Parameter (A_B_CNT) Field Descriptions
503
Channel Destination Address Parameter (DST)
504
Source B Index/Destination B Index Parameter (SRC_DST_BIDX)
504
Channel Destination Address Parameter (DST) Field Descriptions
504
Source B Index/Destination B Index Parameter (SRC_DST_BIDX) Field Descriptions
504
Link Address/B Count Reload Parameter (LINK_BCNTRLD)
505
Link Address/B Count Reload Parameter (LINK_BCNTRLD) Field Descriptions
505
Source C Index/Destination C Index Parameter (SRC_DST_CIDX)
506
C Count Parameter (CCNT)
506
Source C Index/Destination C Index Parameter (SRC_DST_CIDX) Field Descriptions
506
C Count Parameter (CCNT) Field Descriptions
506
16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers
507
Revision ID Register (REVID)
510
EDMA3CC Configuration Register (CCCFG)
510
Revision ID Register (REVID) Field Descriptions
510
EDMA3CC Configuration Register (CCCFG) Field Descriptions
511
QDMA Channel N Mapping Register (Qchmapn)
512
QDMA Channel N Mapping Register (Qchmapn) Field Descriptions
512
DMA Channel Queue Number Register N (Dmaqnumn)
513
DMA Channel Queue Number Register N (Dmaqnumn) Field Descriptions
513
Bits in Dmaqnumn
513
QDMA Channel Queue Number Register (QDMAQNUM)
514
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
514
Event Missed Register (EMR)
515
Event Missed Register (EMR) Field Descriptions
515
Event Missed Clear Register (EMCR)
516
Event Missed Clear Register (EMCR) Field Descriptions
516
QDMA Event Missed Register (QEMR)
517
QDMA Event Missed Register (QEMR) Field Descriptions
517
QDMA Event Missed Clear Register (QEMCR)
518
QDMA Event Missed Clear Register (QEMCR) Field Descriptions
518
EDMA3CC Error Register (CCERR)
519
EDMA3CC Error Register (CCERR) Field Descriptions
519
EDMA3CC Error Clear Register (CCERRCLR)
520
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
520
Error Evaluate Register (EEVAL)
521
Error Evaluate Register (EEVAL) Field Descriptions
521
DMA Region Access Enable Register for Region M (Draem)
522
DMA Region Access Enable Register for Region M (Draem) Field Descriptions
522
QDMA Region Access Enable for Region M (Qraem)
523
QDMA Region Access Enable for Region M (Qraem) Field Descriptions
523
Event Queue Entry Registers (Qxey)
524
Event Queue Entry Registers (Qxey) Field Descriptions
524
Queue N Status Register (Qstatn)
525
Queue N Status Register (Qstatn) Field Descriptions
525
Queue Watermark Threshold a Register (QWMTHRA)
526
Queue Watermark Threshold a Register (QWMTHRA) Field Descriptions
526
EDMA3CC Status Register (CCSTAT)
527
EDMA3CC Status Register (CCSTAT) Field Descriptions
527
Event Register (ER)
529
Event Register (ER) Field Descriptions
529
Event Clear Register (ECR)
530
Event Clear Register (ECR) Field Descriptions
530
Event Set Register (ESR)
531
Event Set Register (ESR) Field Descriptions
531
Chained Event Register (CER)
532
Chained Event Register (CER) Field Descriptions
532
Event Enable Register (EER)
533
Event Enable Register (EER) Field Descriptions
533
Event Enable Clear Register (EECR)
534
Event Enable Set Register (EESR)
534
Event Enable Clear Register (EECR) Field Descriptions
534
Event Enable Set Register (EESR) Field Descriptions
534
Secondary Event Register (SER)
535
Secondary Event Clear Register (SECR)
535
Secondary Event Register (SER) Field Descriptions
535
Secondary Event Clear Register (SECR) Field Descriptions
535
Interrupt Enable Register (IER)
536
Interrupt Enable Register (IER) Field Descriptions
536
Interrupt Enable Clear Register (IECR)
537
Interrupt Enable Set Register (IESR)
537
Interrupt Enable Clear Register (IECR) Field Descriptions
537
Interrupt Enable Set Register (IESR) Field Descriptions
537
Interrupt Pending Register (IPR)
538
Interrupt Pending Register (IPR) Field Descriptions
538
Interrupt Clear Register (ICR)
539
Interrupt Clear Register (ICR) Field Descriptions
539
Interrupt Evaluate Register (IEVAL)
540
Interrupt Evaluate Register (IEVAL) Field Descriptions
540
QDMA Event Register (QER)
541
QDMA Event Register (QER) Field Descriptions
541
QDMA Event Enable Register (QEER)
542
QDMA Event Enable Register (QEER) Field Descriptions
542
QDMA Event Enable Clear Register (QEECR)
543
QDMA Event Enable Set Register (QEESR)
543
QDMA Event Enable Clear Register (QEECR) Field Descriptions
543
QDMA Event Enable Set Register (QEESR) Field Descriptions
543
QDMA Secondary Event Register (QSER)
544
QDMA Secondary Event Register (QSER) Field Descriptions
544
QDMA Secondary Event Clear Register (QSECR)
545
QDMA Secondary Event Clear Register (QSECR) Field Descriptions
545
16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers
546
Revision ID Register (REVID)
547
Revision ID Register (REVID) Field Descriptions
547
EDMA3TC Configuration Register (TCCFG)
548
EDMA3TC Configuration Register (TCCFG) Field Descriptions
548
EDMA3TC Channel Status Register (TCSTAT)
549
EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
549
Error Status Register (ERRSTAT)
550
Error Status Register (ERRSTAT) Field Descriptions
550
Error Enable Register (ERREN)
551
Error Enable Register (ERREN) Field Descriptions
551
Error Clear Register (ERRCLR)
552
Error Clear Register (ERRCLR) Field Descriptions
552
Error Details Register (ERRDET)
553
Error Details Register (ERRDET) Field Descriptions
553
Error Interrupt Command Register (ERRCMD)
554
Error Interrupt Command Register (ERRCMD) Field Descriptions
554
Read Command Rate Register (RDRATE)
555
Read Command Rate Register (RDRATE) Field Descriptions
555
Source Active Options Register (SAOPT)
556
Source Active Options Register (SAOPT) Field Descriptions
556
Source Active Source Address Register (SASRC)
557
Source Active Count Register (SACNT)
557
Source Active Source Address Register (SASRC) Field Descriptions
557
Source Active Count Register (SACNT) Field Descriptions
557
Source Active Destination Address Register (SADST)
558
Source Active B-Index Register (SABIDX)
558
Source Active Destination Address Register (SADST) Field Descriptions
558
Source Active B-Index Register (SABIDX) Field Descriptions
558
Source Active Memory Protection Proxy Register (SAMPPRXY)
559
Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions
559
Source Active Count Reload Register (SACNTRLD)
560
Source Active Source Address B-Reference Register (SASRCBREF)
560
Source Active Count Reload Register (SACNTRLD) Field Descriptions
560
Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
560
Source Active Destination Address B-Reference Register (SADSTBREF)
561
Destination FIFO Set Count Reload Register (DFCNTRLD)
561
Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions
561
Destination FIFO Set Count Reload Register (DFCNTRLD) Field Descriptions
561
Destination FIFO Set Source Address B-Reference Register (DFSRCBREF)
562
Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF)
562
Destination FIFO Set Source Address B-Reference Register (DFSRCBREF) Field Descriptions
562
Destination FIFO Set Destination Address B-Reference Register (DFDSTBREF) Field Descriptions
562
Destination FIFO Options Register N (Dfoptn)
563
Destination FIFO Options Register N (Dfoptn) Field Descriptions
563
Destination FIFO Source Address Register N (Dfsrcn)
564
Destination FIFO Count Register N (Dfcntn)
564
Destination FIFO Source Address Register N (Dfsrcn) Field Descriptions
564
Destination FIFO Count Register N (Dfcntn) Field Descriptions
564
Destination FIFO Destination Address Register N (Dfdstn)
565
Destination FIFO B-Index Register N (Dfbidxn)
565
Destination FIFO Destination Address Register N (Dfdstn) Field Descriptions
565
Destination FIFO B-Index Register N (Dfbidxn) Field Descriptions
565
Destination FIFO Memory Protection Proxy Register N (Dfmpprxyn)
566
Destination FIFO Memory Protection Proxy Register N (Dfmpprxyn) Field Descriptions
566
16.5 Tips
567
16.5.1 Debug Checklist
567
Debug List
567
16.5.2 Miscellaneous Programming/Debug Tips
568
16.6 Setting up a Transfer
569
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Texas Instruments TMS320C6747 DSP Manual (227 pages)
Fixed- and Floating-Point Digital Signal Processor
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 2.64 MB
Table of Contents
1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1
Features
1
Applications
2
Description
2
Functional Block Diagram
4
Table of Contents
5
2 Revision History
6
3 Device Overview
8
Device Characteristics
8
Device Compatibility
9
DSP Subsystem
10
Memory Map Summary
21
Pin Assignments
26
Terminal Functions
28
4 Device Configuration
56
Boot Modes
56
SYSCFG Module
57
Pullup/Pulldown Resistors
59
5 Device Operating Conditions
60
Absolute Maximum Ratings over Operating Case Temperature Range (Unless Otherwise Noted)
60
Handling Ratings
60
Recommended Operating Conditions
61
Notes on Recommended Power-On Hours (POH)
62
Electrical Characteristics over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
63
6 Peripheral Information and Electrical Specifications
64
Parameter Information
64
Recommended Clock and Control Signal Transition Behavior
65
Power Supplies
65
Reset
66
Crystal Oscillator or External Clock Input
69
Clock Plls
71
Interrupts
75
General-Purpose Input/Output (GPIO)
79
Edma
82
External Memory Interface a (EMIFA)
87
External Memory Interface B (EMIFB)
98
Memory Protection Units
106
MMC / Sd / Sdio (Mmcsd)
109
Ethernet Media Access Controller (EMAC)
112
Management Data Input/Output (MDIO)
117
Multichannel Audio Serial Ports (Mcasp0, Mcasp1, and Mcasp2)
119
Serial Peripheral Interface Ports (SPI0, SPI1)
132
Enhanced Capture (Ecap) Peripheral
151
Enhanced Quadrature Encoder (Eqep) Peripheral
154
Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
156
LCD Controller
160
Timers
175
Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
177
Universal Asynchronous Receiver/Transmitter (UART)
182
USB1 Host Controller Registers (USB1.1 OHCI)
184
Usb0 Otg (Usb2.0 Otg)
185
Host-Port Interface (UHPI)
193
Power and Sleep Controller (PSC)
200
Programmable Real-Time Unit Subsystem (PRUSS)
203
Emulation Logic
206
Ieee 1149.1 Jtag
209
Real Time Clock (RTC)
211
Texas Instruments TMS320C6747 DSP User Manual (35 pages)
Processor Universal Serial Bus (USB1.1) OHCI Host Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.31 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
8
Purpose of the Peripheral
8
Architecture
9
Clock and Reset
9
Open Host Controller Interface Functionality
10
Differences from OHCI Specification for USB
10
Implementation of OHCI Specification for USB1.1
11
OHCI Interrupts
12
USB1.1 Host Controller Access to System Memory
12
Physical Addressing
12
Relationships between Virtual Address Physical Address
12
Registers
13
USB1.1 Host Controller Registers
13
OHCI Revision Number Register (HCREVISION)
14
HC Operating Mode Register (HCCONTROL)
14
OHCI Revision Number Register (HCREVISION) Field Descriptions
14
HC Operating Mode Register (HCCONTROL) Field Descriptions
15
HC Command and Status Register (HCCOMMANDSTATUS)
16
HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions
16
HC Interrupt and Status Register (HCINTERRUPTSTATUS)
17
HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions
17
HC Interrupt Enable Register (HCINTERRUPTENABLE)
18
HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions
18
HC Interrupt Disable Register (HCINTERRUPTDISABLE)
19
HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions
19
HC HCAA Address Register (HCHCCA)
20
HC Current Periodic Register (HCPERIODCURRENTED)
20
HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions
20
HC Head Control Register (HCCONTROLHEADED)
21
HC HCAA Address Register (HCHCCA) Field Descriptions
20
HC Head Control Register (HCCONTROLHEADED) Field Descriptions
21
HC Current Control Register (HCCONTROLCURRENTED)
22
HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions
22
HC Head Bulk Register (HCBULKHEADED)
23
HC Current Bulk Register (HCBULKCURRENTED)
23
HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions
23
HC Head Done Register (HCDONEHEAD)
24
HC Frame Interval Register (HCFMINTERVAL)
24
HC Head Bulk Register (HCBULKHEADED) Field Descriptions
23
HC Frame Interval Register (HCFMINTERVAL) Field Descriptions
24
HC Frame Remaining Register (HCFMREMAINING)
25
HC Frame Number Register (HCFMNUMBER)
25
HC Head Done Register (HCDONEHEAD) Field Descriptions
24
HC Frame Number Register (HCFMNUMBER) Field Descriptions
25
HC Periodic Start Register (HCPERIODICSTART)
26
HC Frame Remaining Register (HCFMREMAINING) Field Descriptions
25
HC Periodic Start Register (HCPERIODICSTART) Field Descriptions
26
HC Low-Speed Threshold Register (HCLSTHRESHOLD)
27
HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions
27
HC Root Hub a Register (HCRHDESCRIPTORA)
28
HC Root Hub a Register (HCRHDESCRIPTORA) Field Descriptions
28
HC Root Hub B Register (HCRHDESCRIPTORB)
29
HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions
29
HC Root Hub Status Register (HCRHSTATUS)
30
HC Root Hub Status Register (HCRHSTATUS) Field Descriptions
30
HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
31
HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions
31
HC Port 2 Status and Control Register (HCRHPORTSTATUS2)
33
HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions
33
Important Notice
35
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