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4.8
Interrupt Masked Register (IMR)
The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt
condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR
bit is set. The IMR bit is not set if the interrupt is not enabled in IMSR. The IMR is shown in
described in
Table
31
15
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Bit
Field
Value
31-3
Reserved
0
2
LTM
0
1
1-0
Reserved
0
SPRUEQ4C – February 2009
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28.
Figure 26. Interrupt Masked Register (IMR)
Reserved
R-0
Table 28. Interrupt Masked Register (IMR) Field Descriptions
Description
Reserved
Line trap masked. Write a 1 to clear LTM and the LT bit in the interrupt raw register (IRR); a write of 0
has no effect.
A line trap condition has not occurred.
Illegal memory access type (only set if the LTMSET bit in IMSR is set). See
details.
Reserved
Reserved
R-0
Registers
Figure 26
and
16
3
2
1
0
LTM
Reserved
R/W1C-0
R-0
Section 2.13
for more
DDR2 Memory Controller
47
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