Hc Interrupt And Status Register (Hcinterruptstatus); Hc Interrupt And Status Register (Hcinterruptstatus) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

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3.4

HC Interrupt and Status Register (HCINTERRUPTSTATUS)

The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB1.1 host
controller internal interrupt sources. HCINTERRUPTSTATUS is shown in
Table 5.
Figure 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS)
31 30 29
Rsvd OC
R-0 R-0
15
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions
Bit Field Value
31 Reserved 0
30 OC 0-1
29-7 Reserved 0
6 RHSC
0
1
5 FNO
0
1
4 UE
0
1
3 RD
0
1
2 SF
0
1
1 WDH
0
1
0 SO
0
1
SPRUFM8 – June 2009
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Reserved
R-0
Description
Reserved
Ownership change.
Reserved
Root hub status change. A write of 1 clears this bit; a write of 0 has no effect.
A root hub status change has not occurred.
A root hub status change has occurred.
Frame number overflow. A write of 1 clears this bit; a write of 0 has no effect.
A frame number overflow has not occurred.
A frame number overflow has occurred.
Unrecoverable error. A write of 1 clears this bit; a write of 0 has no effect.
An unrecoverable error has not occurred.
An unrecoverable error has occurred on the OCPI bus, or that an isochronous TD PSW field condition
code was not set to Not Accessed when the USB1.1 host controller attempted to perform a transfer
using that PSW/offset pair.
Resume detected. A write of 1 clears this bit; a write of 0 has no effect.
A downstream device has not issued a resume request.
A downstream device has issued a resume request.
Start of frame. A write of 1 clears this bit; a write of 0 has no effect.
A SOF has not been issued.
A SOF has been issued.
Write done head. The host controller driver must read the value from the HC head done register
(HCDONEHEAD) before writing 1 to this bit. A write of 1 clears this bit; a write of 0 has no effect.
USB1.1 host controller has not updated the HC head done register (HCDONEHEAD).
USB1.1 host controller has updated the HC head done register (HCDONEHEAD).
Scheduling overrun. A write of 1 clears this bit; a write of 0 has no effect.
A scheduling overrun has not occurred.
A scheduling overrun has occurred.
Figure 5
Reserved
R-0
7 6 5 4
RHSC FNO UE
R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0
Universal Serial Bus OHCI Host Controller
Registers
and described in
16
3 2 1 0
RD SF WDH SO
17