Trip-Zone Control Register (Tzctl); Trip-Zone Enable Interrupt Register (Tzeint); Trip-Zone Control Register (Tzctl) Field Descriptions; Trip-Zone Enable Interrupt Register (Tzeint) Field Descriptions - Texas Instruments TMS320x2833x Reference Manual

Enhanced pulse width modulator (epwm) module
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Registers
Table 38. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions (continued)
Bits
Name
1
CBC2
0
CBC1
15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bits
Name
15–4
Reserved
3–2
TZB
1–0
TZA
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
Bits
Name
15-3
Reserved
2
OST
106 TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM) Module
Value
Description
Trip-zone 2 (TZ2) Select
0
Disable TZ2 as a CBC trip source for this ePWM module
1
Enable TZ2 as a CBC trip source for this ePWM module
Trip-zone 1 (TZ1) Select
0
Disable TZ1 as a CBC trip source for this ePWM module
1
Enable TZ1 as a CBC trip source for this ePWM module
Figure 81. Trip-Zone Control Register (TZCTL)
4
R-0
Table 39. Trip-Zone Control Register (TZCTL) Field Descriptions
Value
Description
Reserved
When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins
can cause an event is defined in the TZSEL register.
00
High impedance (EPWMxB = High-impedance state)
01
Force EPWMxB to a high state
10
Force EPWMxB to a low state
11
Do nothing, no action is taken on EPWMxB.
When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins
can cause an event is defined in the TZSEL register.
00
High impedance (EPWMxA = High-impedance state)
01
Force EPWMxA to a high state
10
Force EPWMxA to a low state
11
Do nothing, no action is taken on EPWMxA.
Figure 82. Trip-Zone Enable Interrupt Register (TZEINT)
Reserved
R-0
Value
Description
Reserved
Trip-zone One-Shot Interrupt Enable
0
Disable one-shot interrupt generation
1
Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.
© 2008–2009, Texas Instruments Incorporated
Reserved
R-0
3
2
TZB
R/W-0
Reserved
R -0
3
2
OST
R/W-0
SPRUG04A – October 2008 – Revised July 2009
www.ti.com
8
1
0
TZA
R/W-0
8
1
0
CBC
Reserved
R/W-0
R-0
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