Texas Instruments MSMC Manuals

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Texas Instruments MSMC User Manual (57 pages)

KeyStone Architecture Multicore Shared Memory Controller

Brand: Texas Instruments | Category: Controller | Size: 0.7 MB

Release History
2
Table of Contents
3
List of Tables
5
Ø-VII
7
About this Manual
7
Notational Conventions
7
Related Documentation from Texas Instruments
8
Trademarks
8
Introduction
9
Overview
10
Terminology
10
Features
10
MSMC Architecture
11
Functional Overview
12
C66X Corepac Slave Interfaces
12
System Slave Interfaces
12
MSMC Functional Block Diagram
12
System EMIF Access Slave Interface (SES)
13
System MSMC SRAM Access Slave Interface (SMS)
13
System Master Interface
13
External Memory Master Interface
13
Memory Protection and Address Extension (MPAX)
14
MPAX Segment Operation
14
MPAX Segment Register Set Layout
15
MPAX Segment Register Reset Values
16
Memory Protection
16
MPAX Segment Size Encoding
16
Memory Protection Fault Reporting
18
Address Extension
18
Table 2-2 MSMC Protection Fault Reporting Register List
18
Table 2-3 Replacement Address Used as Per-Segment Size
18
SES Aliased Access to MSMC RAM
19
SMS MPAX Address Extension
19
Address Extension Error Reporting
19
MSMC Memory
20
Msmc Sram
20
MSMC Memory Banking
20
MSMC SRAM Bank Addressing
20
MSMC Bandwidth Management
21
Starvation Counters Per Requestor
21
MSMC Register Access Control
22
MSMC Configuration Write Lock Register List
22
Error Detection and Correction Support
24
Parity Generation and Checking
24
EDC Operation
24
Error Detection and Correction
24
Error Correction Mode
25
MSMC EDC Register List
25
Soft Error Correction Actions
25
EDC Error Reporting
26
Background Parity Refresh-Scrubbing
26
Scrubbing Rate
26
Scrubbing Error Logging and Statistics Collection
27
Parity RAM Initialization at Reset
27
MSMC Interrupt Control
28
MSMC Interrupt Control Register List
28
Reset Considerations
29
Memory Map
30
SPRUGW7-November 2010
30
Keystone Architecture Multicore Shared Memory Controller (MSMC) User Guide
30
MSMC Memory Map for TCI6616
30
MSMC Memory Map for TCI6608
30
MSMC Registers
31
MSMC Memory Mapped Registers
31
MSMC Memory Mapped Registers
32
Peripheral Identification Register (PID)
34
Peripheral ID Register (PID) Field Descriptions
34
Peripheral ID Register (PID)
34
EDC Registers
35
MSMC SRAM EDC Control Register (SMEDCC)
35
MSMC SRAM Correctable EDC Error Address Register (SMCERRAR)
35
Table 3-3 MSMC SRAM EDC Control Register (SMEDCC) Field Descriptions
35
Table 3-4 MSMC SRAM Correctable EDC Error Address Register (SMCERRAR) Field Descriptions
35
Figure 3-3 MSMC SRAM Correctable EDC Error Address Register (SMCERRAR)
35
MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR)
36
MSMC SRAM Non-Correctable EDC Error Address Register (SMNCERRAR)
36
Table 3-5 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR) Field Descriptions
36
Table 3-6 MSMC SRAM Non-Correctable EDC Error Address Register (SMNCERRAR) Field Descriptions
36
Figure 3-4 MSMC SRAM Correctable EDC Extended Error Register (SMCERRXR)
36
Figure 3-5 MSMC SRAM Non-Correctable EDC Error Address Register (SMNCERRAR)
36
MSMC SRAM Non-Correctable EDC Extended Error Register (SMNCERRXR)
37
MSMC Scrubbing Error Corrected Address Register (SMCEA)
37
Table 3-7 MSMC SRAM Non-Correctable EDC Extended Error Register (SMNCERRXR) Field Descriptions
37
Table 3-8 MSMC Scrubbing Error Corrected Address Register (SMCEA) Field Descriptions
37
Figure 3-6 MSMC SRAM Non-Correctable EDC Extended Error Register (SMNCERRXR)
37
Figure 3-7 MSMC Scrubbing Error Corrected Address Register (SMCEA)
37
MSMC Scrubbing Non-Correctable Address Register (SMNCEA)
38
MSMC Scrubbing Error Counter Register (SMSECC)
38
Table 3-9 MSMC Scrubbing Non-Correctable Address Register (SMNCEA) Field Descriptions
38
Table 3-10 MSMC Scrubbing Error Corrected Counter Register (SMSECC) Field Descriptions
38
Figure 3-8 MSMC Scrubbing Non-Correctable Address Register (SMNCEA)
38
Figure 3-9 MSMC Scrubbing Error Corrected Counter Register (SMSECC)
38
Bandwidth Management Control Registers
39
Starvation Bound Register for C66X Corepac Slave Ports (Sbndcn)
39
Starvation Bound Register for SMS Port (SBNDM)
39
Starvation Bound Register for SES Port (SBNDE)
40
Table 3-13 Starvation Bound Register for SES Port (SBNDE) Field Descriptions
40
MPAX Segment Registers
41
Sms_Mpaxhn
41
Sms_Mpaxln
41
Ses_Mpaxhn
42
Ses_Mpaxln
42
Memory Protection Fault Reporting Registers
44
MSMC Memory Protection Fault Address Register (SMPFAR)
44
MSMC Memory Protection Fault Extension Register (SMPFXR)
44
MSMC Memory Protection Fault Requestor Register (SMPFR)
44
Table 3-18 MSMC Memory Protection Fault Address Register (SMPFAR) Field Descriptions
44
Table 3-19 MSMC Memory Protection Fault Extension Register (SMPFXR) Field Descriptions
44
Table 3-20 MSMC Memory Protection Fault Requestor Register (SMPFR) Field Descriptions
44
Figure 3-17 MSMC Memory Protection Fault Address Register (SMPFAR)
44
Figure 3-18 MSMC Memory Protection Fault Extension Register (SMPFXR)
44
Figure 3-19 MSMC Memory Protection Fault Requestor Register (SMPFR)
44
MSMC Memory Protection Fault Control Register (SMPFCR)
45
Table 3-21 MSMC Memory Protection Fault Control Register (SMPFCR) Field Descriptions
45
Figure 3-20 MSMC Memory Protection Fault Control Register (SMPFCR)
45
MSMC Configuration Write Lock Registers
46
Configuration Lock Control for Non-MPAX Registers (CFGLCK)
46
Configuration Unlock Control for Non-MPAX Registers (CFGULCK)
46
Configuration Lock Status for Non-MPAX Registers (CFGLCKSTAT)
47
Configuration Lock Control for SMS MPAX Registers (SMS_MPAX_LCK)
47
Configuration Unlock Control for SMS MPAX Registers (SMS_MPAX_ULCK)
48
Configuration Lock Status for SMS MPAX Registers (SMS_MPAX_LCKSTAT)
48
Configuration Lock Control for SES MPAX Registers (SES_MPAX_LCK)
49
Configuration Unlock Control for SES MPAX Registers (SES_MPAX_ULCK)
49
Configuration Lock Status for SES MPAX Registers (SES_MPAX_LCKSTAT)
50
MSMC Interrupt Control Registers
51
Interrupt Enabled Status Register (SMESTAT)
51
Interrupt Raw Status Register (SMIRSTAT)
52
Table 3-32 Interrupt Enabled Status Register (SMIRSTAT) Field Descriptions
52
Interrupt Raw Status Clear Register (SMIRC)
53
Interrupt Enable Status Register (SMIESTAT)
53
Table 3-33 Interrupt Raw Status Clear Register (SMIRC) Field Descriptions
53
Table 3-34 Interrupt Enabled Status Register (SMIESTAT) Field Descriptions
53
Interrupt Enable Clear Register (SMIEC)
54
Table 3-35 Interrupt Enable Clear Register (SMIEC) Field Descriptions
54
Index
56

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