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3.8 MSMC Interrupt Control Registers
3.8.1 Interrupt Enabled Status Register (SMESTAT)
Figure 3-30
Interrupt Enabled Status Register (SMESTAT)
31
R +0000 0000 0000 0000
Legend: R = Read only; W = Write only; -n = value after reset; -x, value is indeterminate — see the device-specific data manual
Table 3-31
Interrupt Enabled Status Register (SMESTAT) Field Descriptions
Bit
Field
31-16
PFESTAT
15-4
Reserved
3
CEES
2
NCEES
1
CSES
0
NCSES
End of Table 3-31
SPRUGW7—November 2010
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The SMESTAT register provides the status of those interrupts that are enabled i.e. a
bitfield in the SMESTAT register is set if the associated interrupt is both enabled and
has occurred.
The SMESTAT is shown in
PFESTAT
Value
Description
0-FFFFh
Bit n denotes the protection fault interrupt is enabled and pending for PrivID n.
0
Reads return 0 and writes have no effect.
0
No EDC error.
1
Correctable EDC error interrupt is enabled and pending.
0
No EDC error.
1
Non-correctable EDC error interrupt is enabled and pending.
0
No scrubbing error.
1
Correctable scrubbing error interrupt is enabled and pending.
0
No scrubbing error.
1
Non-correctable scrubbing error interrupt is enabled and pending.
KeyStone Architecture Multicore Shared Memory Controller (MSMC) User Guide
Figure 3-30
and described in
16 15
Reserved
R +0000 0000 0000
3.8 MSMC Interrupt Control Registers
Chapter 3—MSMC Registers
Table
3-31.
4
3
2
1
CEES
NCEES
CSES
R +0
R +0
R +0
0
NCSES
R +0
3-21
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