Global Interrupt Mask Register (Cangim); Global Interrupt Mask Register (Cangim) Field Descriptions - Texas Instruments TMS320x281 series Reference Manual

Interrupt Registers

2.15.2 Global Interrupt Mask Register (CANGIM)

The set up for the interrupt mask register is the same as for the interrupt flag register. If a bit is set, the
corresponding interrupt is enabled. This register is EALLOW protected.
31
15 14
Reserved AAIM
R-0 R/WP-0
7
LEGEND: R = Read; W = Write; WP = Write in EALLOW mode only; -n = value after reset
Table 2-15. Global Interrupt Mask Register (CANGIM) Field Descriptions
Bit Field
31:18 Reserved
17 MTOM
16 TCOM
15 Reserved
14 AAIM
13 WDIM
12 WUIM
11 RMLIM
10 BOIM
9 EPIM
48 eCAN Registers
Figure 2-18. Global Interrupt Mask Register (CANGIM)
Reserved
R-0
13 12
WDIM WUIM
R/WP-0 R/WP-0
Reserved
R-0
Value Description
Reads are undefined and writes have no effect.
Mailbox time-out interrupt mask
1 Enabled
0 Disabled
Time stamp counter overflow mask
1 Enabled
0 Disabled
Reads are undefined and writes have no effect.
Abort Acknowledge Interrupt Mask.
1 Enabled
0 Disabled
Write denied interrupt mask
1 Enabled
0 Disabled
Wake-up interrupt mask
1 Enabled
0 Disabled
Received-message-lost interrupt mask
1 Enabled
0 Disabled
Bus-off interrupt mask
1 Enabled
0 Disabled
Error-passive interrupt mask
1 Enabled
0 Disabled
11 10
RMLIM BOIM
R/WP-0 R/WP-0
3 2
GIL
R/WP-0
SPRU074F – May 2002 – Revised January 2009
www.ti.com
18 17 16
MTOM TCOM
R/WP- R/WP-
0 0
9 8
EPIM WLIM
R/WP-0 R/WP-0
1 0
I1EN I0EN
R/WP-0 R/WP-0
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