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4.6
Peripheral Bus Burst Priority Register (PBBPR)
The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the DDR2
memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the
priority of the oldest command in the command FIFO after a set number of transfers have been made.
The PR_OLD_COUNT bit sets the number of transfers that must be made before the DDR2 memory
controller raises the priority of the oldest command. The PBBPR is shown in
Table
26. See
Section 2.7.2
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
Bit
Field
31-8
Reserved
7-0
PR_OLD_COUNT
SPRUEQ4C – February 2009
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for more details on command starvation.
Figure 24. Peripheral Bus Burst Priority Register (PBBPR)
R-0
Value
Description
0
Reserved
0-FFh
Priority raise old counter. Specifies the number of memory transfers after which the DDR2
memory controller elevates the priority of the oldest command in the command FIFO.
0
1 memory transfer
1h
2 memory transfers
2h
3 memory transfers
3h-FFh 4 to 256 memory transfers
Reserved
R-0
8
7
Figure 24
and described in
PR_OLD_COUNT
R/W-FFh
DDR2 Memory Controller
Registers
16
0
45
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