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Texas Instruments TMS320x2833 series Manuals
Manuals and User Guides for Texas Instruments TMS320x2833 series. We have
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Texas Instruments TMS320x2833 series manual available for free PDF download: Reference Manual
Texas Instruments TMS320x2833 series Reference Manual (152 pages)
System Control and Interrupts
Brand:
Texas Instruments
| Category:
Controller
| Size: 1.2 MB
Table of Contents
Table of Contents
3
List of Figures
5
Preface
11
1 Flash and OTP Memory Blocks
15
Flash and OTP Memory
16
1.1.1 Flash Memory
16
1.1.2 OTP Memory
16
Flash and OTP Power Modes
16
1.2.1 Flash and OTP Performance
18
1.2.2 Flash Pipeline Mode
18
1.2.3 Reserved Locations Within Flash and OTP
19
Flash Pipeline
19
1.2.4 Procedure to Change the Flash Configuration Registers
20
Flash Configuration Access Flow Diagram
20
Flash and OTP Registers
21
Flash/Otp Configuration Registers
21
Flash Options Register (FOPT)
22
Flash Power Register (FPWR)
22
Flash Options Register (FOPT) Field Descriptions
22
Flash Power Register (FPWR) Field Descriptions
22
Flash Status Register (FSTATUS)
23
Flash Status Register (FSTATUS) Field Descriptions
23
Flash Standby Wait Register (FSTDBYWAIT)
24
Flash Standby to Active Wait Counter Register (FACTIVEWAIT)
24
Flash Standby Wait Register (FSTDBYWAIT) Field Descriptions
24
Flash Standby to Active Wait Counter Register (FACTIVEWAIT) Field Descriptions
24
Flash Wait-State Register (FBANKWAIT)
25
Flash Wait-State Register (FBANKWAIT) Field Descriptions
25
OTP Wait-State Register (FOTPWAIT)
26
OTP Wait-State Register (FOTPWAIT) Field Descriptions
26
2 Code Security Module (CSM)
27
Functional Description
28
Security Levels
28
CSM Impact on Other On-Chip Resources
30
Resources Affected by the CSM
30
Resources Not Affected by the CSM
30
Incorporating Code Security in User Applications
31
Code Security Module (CSM) Registers
31
2.3.1 Environments that Require Security Unlocking
32
CSM Status and Control Register (CSMSCR)
32
CSM Status and Control Register (CSMSCR) Field Descriptions
32
2.3.2 Password Match Flow
33
Password Match Flow (PMF)
33
2.3.3 Unsecuring Considerations for Devices With/Without Code Security
34
Do's and Don'ts to Protect Security Logic
36
2.4.1 Do's
36
2.4.2 Don'ts
36
CSM Features - Summary
36
3 Clocking
37
Clocking and System Control
38
Clock and Reset Domains
38
Peripheral Clock Control 0 Register (PCLKCR0)
39
PLL, Clocking, Watchdog, and Low-Power Mode Registers
39
Peripheral Clock Control 0 Register (PCLKCR0) Field Descriptions
39
Peripheral Clock Control 1 Register (PCLKCR1)
40
Peripheral Clock Control 1 Register (PCLKCR1) Field Descriptions
41
Peripheral Clock Control 3 Register (PCLKCR3)
43
Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions
43
High-Speed Peripheral Clock Prescaler (HISPCP) Register
44
Low-Speed Peripheral Clock Prescaler Register (LOSPCP)
44
High-Speed Peripheral Clock Prescaler (HISPCP) Field Descriptions
44
Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions
44
OSC and PLL Block
45
3.2.1 PLL-Based Clock Module
45
3.2.2 Main Oscillator Fail Detection
46
Oscillator Fail-Detection Logic Diagram
46
Possible PLL Configuration Modes
46
3.2.3 XCLKOUT Generation
48
3.2.4 PLL Control (PLLCR) Register
49
PLLCR Change Procedure Flow Chart
50
3.2.5 PLL Control, Status and XCLKOUT Register Descriptions
51
PLLCR Register Layout
51
PLL Status Register (PLLSTS)
51
PLLCR Bit Descriptions
51
PLL Status Register (PLLSTS) Field Descriptions
51
3.2.6 External Reference Oscillator Clock Option
52
Low-Power Modes Block
53
Low-Power Mode Summary
53
Low Power Modes
53
Low Power Mode Control 0 Register (LPMCR0)
54
Low Power Mode Control 0 Register (LPMCR0) Field Descriptions
54
Watchdog Block
55
Watchdog Module
55
3.4.1 Servicing the Watchdog Timer
56
3.4.2 Watchdog Reset or Watchdog Interrupt Mode
56
Example Watchdog Key Sequences
56
3.4.3 Watchdog Operation in Low Power Modes
57
3.4.4 Emulation Considerations
57
3.4.5 Watchdog Registers
58
System Control and Status Register (SCSR)
58
System Control and Status Register (SCSR) Field Descriptions
58
Watchdog Counter Register (WDCNTR)
59
Watchdog Reset Key Register (WDKEY)
59
Watchdog Control Register (WDCR)
59
Watchdog Counter Register (WDCNTR) Field Descriptions
59
Watchdog Reset Key Register (WDKEY) Field Descriptions
59
Watchdog Control Register (WDCR) Field Descriptions
59
32-Bit CPU Timers 0/1/2
60
CPU-Timers
60
CPU-Timer Interrupts Signals and Output Signal
61
CPU-Timers 0, 1, 2 Configuration and Control Registers
61
Timerxtim Register (X = 0, 1, 2)
62
Timerxtimh Register (X = 0, 1, 2)
62
Timerxprd Register (X = 0, 1, 2)
62
Timerxprdh Register (X = 0, 1, 2)
62
Timerxtim Register Field Descriptions
62
Timerxtimh Register Field Descriptions
62
Timerxprd Register Field Descriptions
62
Timerxtcr Register (X = 0, 1, 2)
63
Timerxprdh Register Field Descriptions
63
Timerxtcr Register Field Descriptions
63
Timerxtpr Register (X = 0, 1, 2)
64
Timerxtprh Register (X = 0, 1, 2)
64
Timerxtpr Register Field Descriptions
64
Timerxtprh Register Field Descriptions
64
4 General-Purpose Input/Output (GPIO)
65
GPIO Module Overview
66
GPIO0 to GPIO27 Multiplexing Diagram
66
GPIO28 to GPIO31 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged)
67
GPIO32, GPIO33 Multiplexing Diagram
68
GPIO34 to GPIO63 Multiplexing Diagram (Peripheral 2 and Peripheral 3 Outputs Merged)
69
GPIO64 to GPIO79 Multiplexing Diagram (Minimal Gpios Without Qualification)
70
Configuration Overview
71
GPIO Control Registers
71
GPIO Interrupt and Low Power Mode Select Registers
71
Digital General Purpose I/O Control
72
GPIO Data Registers
73
Input Qualification
74
No Synchronization (Asynchronous Input)
74
4.4.2 Synchronization to SYSCLKOUT Only
74
4.4.3 Qualification Using a Sampling Window
74
Input Qualification Using a Sampling Window
74
Sampling Period
75
Sampling Frequency
75
Case 1: Three-Sample Sampling Window Width
76
Case 2: Six-Sample Sampling Window Width
76
Input Qualifier Clock Cycles
77
GPIO and Peripheral Multiplexing (MUX)
78
Default State of Peripheral Input
79
Gpioa Mux
80
Gpiob Mux
81
Gpioc Mux
82
Register Bit Definitions
83
GPIO Port a MUX 1 (GPAMUX1) Register
83
GPIO Port a Multiplexing 1 (GPAMUX1) Register Field Descriptions
83
GPIO Port a MUX 2 (GPAMUX2) Register
85
GPIO Port a MUX 2 (GPAMUX2) Register Field Descriptions
85
GPIO Port B MUX 1 (GPBMUX1) Register
87
GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions
87
GPIO Port B MUX 2 (GPBMUX2) Register
89
GPIO Port B MUX 2 (GPBMUX2) Register Field Descriptions
89
GPIO Port C MUX 1 (GPCMUX1) Register
91
GPIO Port C MUX 1 (GPCMUX1) Register Field Descriptions
91
GPIO Port C MUX 2 (GPCMUX2) Register
92
GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions
92
GPIO Port a Qualification Control (GPACTRL) Register
94
GPIO Port a Qualification Control (GPACTRL) Register Field Descriptions
94
GPIO Port B Qualification Control (GPBCTRL) Register
95
GPIO Port B Qualification Control (GPBCTRL) Register Field Descriptions
95
GPIO Port a Qualification Select 1 (GPAQSEL1) Register
96
GPIO Port a Qualification Select 2 (GPAQSEL2) Register
96
GPIO Port a Qualification Select 1 (GPAQSEL1) Register Field Descriptions
96
GPIO Port a Qualification Select 2 (GPAQSEL2) Register Field Descriptions
96
GPIO Port B Qualification Select 1 (GPBQSEL1) Register
97
GPIO Port B Qualification Select 2 (GPBQSEL2) Register
97
GPIO Port B Qualification Select 1 (GPBQSEL1) Register Field Descriptions
97
GPIO Port B Qualification Select 2 (GPBQSEL2) Register Field Descriptions
97
GPIO Port a Direction (GPADIR) Register
98
GPIO Port B Direction (GPBDIR) Register
98
GPIO Port a Direction (GPADIR) Register Field Descriptions
98
GPIO Port C Direction (GPCDIR) Register
99
GPIO Port B Direction (GPBDIR) Register Field Descriptions
99
GPIO Port C Direction (GPCDIR) Register Field Descriptions
99
GPIO Port a Pullup Disable (GPAPUD) Registers
100
GPIO Port B Pullup Disable (GPBPUD) Registers
100
GPIO Port a Internal Pullup Disable (GPAPUD) Register Field Descriptions
100
GPIO Port B Internal Pullup Disable (GPBPUD) Register Field Descriptions
100
GPIO Port C Pullup Disable (GPCPUD) Registers
101
GPIO Port a Data (GPADAT) Register
101
GPIO Port C Internal Pullup Disable (GPCPUD) Register Field Descriptions
101
GPIO Port B Data (GPBDAT) Register
102
GPIO Port a Data (GPADAT) Register Field Descriptions
102
GPIO Port B Data (GPBDAT) Register Field Descriptions
102
GPIO Port C Data (GPCDAT) Register
103
GPIO Port C Data (GPCDAT) Register Field Descriptions
103
GPIO Port a Set, Clear and Toggle (GPASET, GPACLEAR, GPATOGGLE) Registers
104
GPIO Port a Set (GPASET) Register Field Descriptions
104
GPIO Port a Clear (GPACLEAR) Register Field Descriptions
104
GPIO Port a Toggle (GPATOGGLE) Register Field Descriptions
104
GPIO Port B Set, Clear and Toggle (GPBSET, GPBCLEAR, GPBTOGGLE) Registers
105
GPIO Port B Set (GPBSET) Register Field Descriptions
105
GPIO Port B Clear (GPBCLEAR) Register Field Descriptions
105
GPIO Port B Toggle (GPBTOGGLE) Register Field Descriptions
105
GPIO Port C Set, Clear and Toggle (GPCSET, GPCCLEAR, GPCTOGGLE) Registers
106
GPIO Port C Set (GPCSET) Register Field Descriptions
106
GPIO Port C Clear (GPCCLEAR) Register Field Descriptions
106
GPIO Port C Toggle (GPCTOGGLE) Register Field Descriptions
106
GPIO Xintn, XNMI Interrupt Select (Gpioxintnsel, GPIOXNMISEL) Registers
107
GPIO Xintn Interrupt Select (Gpioxintnsel) Register Field Descriptions
107
XINT1/XINT2 Interrupt Select and Configuration Registers
107
GPIO XINT3 - XINT7 Interrupt Select (Gpioxintnsel) Register Field Descriptions
107
XINT3 - XINT7 Interrupt Select and Configuration Registers
107
GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register
108
GPIO XNMI Interrupt Select (GPIOXNMISEL) Register Field Descriptions
108
GPIO Low Power Mode Wakeup Select (GPIOLPMSEL) Register Field Descriptions
108
5 Peripheral Frames
109
Peripheral Frame Registers
110
Peripheral Frame 0 Registers
110
Peripheral Frame 1 Registers
110
Peripheral Frame 2 Registers
111
Peripheral Frame 3 Registers
111
EALLOW-Protected Registers
112
Access to EALLOW-Protected Registers
112
EALLOW-Protected Device Emulation Registers
112
EALLOW-Protected Flash/Otp Configuration Registers
112
EALLOW-Protected Code Security Module (CSM) Registers
113
EALLOW-Protected PIE Vector Table
113
EALLOW-Protected PLL, Clocking, Watchdog, and Low-Power Mode Registers
114
EALLOW-Protected GPIO MUX Registers
114
EALLOW-Protected Ecan Registers
115
EALLOW-Protected Epwm1 - Epwm6 Registers
115
XINTF Registers
115
Device Emulation Registers
116
Device Configuration (DEVICECNF) Register
116
DEVICECNF Register Field Descriptions
116
Part ID Register
117
CLASSID Register
117
REVID Register
117
PARTID Register Field Descriptions
117
CLASSID Register Description
117
Write-Followed-By-Read Protection
118
REVID Register Field Descriptions
118
PROTSTART and PROTRANGE Registers
118
PROTSTART Valid Values
118
PROTRANGE Valid Values
119
6 Peripheral Interrupt Expansion (PIE)
121
Overview of the PIE Controller
122
6.1.1 Interrupt Operation Sequence
122
Overview: Multiplexing of Interrupts Using the PIE Block
122
Typical PIE/CPU Interrupt Response - Intx.y
124
Enabling Interrupt
124
Vector Table Mapping
125
Interrupt Vector Table Mapping
125
Vector Table Mapping after Reset Operation
125
Reset Flow Diagram
126
Interrupt Sources
127
PIE Interrupt Sources and External Interrupts XINT1/XINT2
127
PIE Interrupt Sources and External Interrupts (XINT3 - XINT7)
128
6.3.1 Procedure for Handling Multiplexed Interrupts
129
6.3.2 Procedures for Enabling and Disabling Multiplexed Peripheral Interrupts
130
6.3.3 Flow of a Multiplexed Interrupt Request from a Peripheral to the CPU
131
Multiplexed Interrupt Request Flow Diagram
131
6.3.4 the PIE Vector Table
132
PIE Muxed Peripheral Interrupt Vector Table
133
PIE Vector Table
134
PIE Configuration Registers
139
PIE Configuration and Control Registers
139
PIE Interrupt Registers
140
PIECTRL Register (Address CE0)
140
PIE Interrupt Acknowledge Register (PIEACK) Register (Address CE1)
140
PIECTRL Register Address Field Descriptions
140
PIE Interrupt Acknowledge Register (PIEACK) Field Descriptions
140
6.5.1 PIE Interrupt Flag Registers
141
PIE Interrupt Enable Registers
141
Pieifrx Register (X = 1 to 12)
141
Pieierx Register (X = 1 to 12)
141
Pieifrx Register Field Descriptions
141
CPU Interrupt Flag Register (IFR)
142
Pieierx Register (X = 1 to 12) Field Descriptions
142
Interrupt Flag Register (IFR) - CPU Register
143
Interrupt Flag Register (IFR) - CPU Register Field Descriptions
143
Interrupt Enable Register (IER) and Debug Interrupt Enable Register (DBGIER)
144
Interrupt Enable Register (IER) - CPU Register
145
Interrupt Enable Register (IER) - CPU Register Field Descriptions
145
Debug Interrupt Enable Register (DBGIER) - CPU Register
146
Debug Interrupt Enable Register (DBGIER) - CPU Register Field Descriptions
146
External Interrupt Control Registers
148
External Interrupt N Control Register (Xintncr)
148
External NMI Interrupt Control Register (XNMICR) - Address 7077H
148
External Interrupt N Control Register (Xintncr) Field Descriptions
148
External NMI Interrupt Control Register (XNMICR) Field Descriptions
148
External Interrupt 1 Counter (XINT1CTR) (Address 7078H)
149
External Interrupt 2 Counter (XINT2CTR) (Address 7079H)
149
XNMICR Register Settings and Interrupt Sources
149
External Interrupt 1 Counter (XINT1CTR) Field Descriptions
149
External NMI Interrupt Counter (XNMICTR) (Address 707Fh)
150
External Interrupt 2 Counter (XINT2CTR) Field Descriptions
150
External NMI Interrupt Counter (XNMICTR) Field Descriptions
150
Revision History
151
Changes Made in this Revision
151
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