Registers; Sdram Status Register (Sdrstat); Ddr2 Memory Controller Registers; Sdram Status Register (Sdrstat) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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4

Registers

Table 20 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data
manual for the memory address of these registers.
Offset Acronym
4h SDRSTAT
8h SDBCR
Ch SDRCR
10h SDTIMR
14h SDTIMR2
20h PBBPR
C0h IRR
C4h IMR
C8h IMSR
CCh IMCR
E4h DDRPHYCR
F0h VTPIOCR
4.1

SDRAM Status Register (SDRSTAT)

The SDRAM status register (SDRSTAT) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field Value
31-3 Reserved 0
2 PHYRDY
0
1
1-0 Reserved 0
SPRUEQ4C – February 2009
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Table 20. DDR2 Memory Controller Registers
Register Description
SDRAM Status Register
SDRAM Bank Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register
SDRAM Timing Register 2
Peripheral Bus Burst Priority Register
Interrupt Raw Register
Interrupt Masked Register
Interrupt Mask Set Register
Interrupt Mask Clear Register
DDR PHY Control Register
DDR VTP IO Control Register
Figure 19. SDRAM Status Register (SDRSTAT)
Reserved
R-0
Table 21. SDRAM Status Register (SDRSTAT) Field Descriptions
Description
Reserved
DDR PHY ready.
DDR PHY is not ready.
DDR PHY is ready for operation.
Reserved
Figure 19 and described in
Reserved
R-4000h
Registers
Section
Section 4.1
Section 4.2
Section 4.3
Section 4.4
Section 4.5
Section 4.6
Section 4.7
Section 4.8
Section 4.9
Section 4.10
Section 4.11
Section 4.12
Table 21.
16
3 2 1 0
PHYRDY Reserved
R-1 R-0
DDR2 Memory Controller 39