Edma Channel Interrupt Pending Low Register (Ciprl) Field Descriptions - Texas Instruments TMS320C6000 DSP Reference Manual

EDMA Control Registers
4.7.3 EDMA Channel Interrupt Pending Registers (CIPRL, CIPRH)
4.7.3.1 EDMA Channel Interrupt Pending Low Register (CIPRL)
Figure 4−5. EDMA Channel Interrupt Pending Low Register (CIPRL)
31 30
CIP31 CIP30
R/W-0 R/W-0
23 22
CIP23 CIP22
R/W-0 R/W-0
15 14
CIP15 CIP14
R/W-0 R/W-0
7 6
CIP7 CIP6
R/W-0 R/W-0
Legend: R/W = Read/Write; -n = value after reset
Table 4−9. EDMA Channel Interrupt Pending Low Register (CIPRL) Field Descriptions
Bit Field symval
31−0 CIP OF(value)
DEFAULT
−
†
For CSL implementation, use the notation EDMA_CIPRL_CIP_symval.
4-16 TMS320C64x EDMA
The EDMA channel interrupt pending registers (CIPRL and CIPRH) are shown
in Figure 4−5 and Figure 4−6 and described in Table 4−9 and Table 4−10.
29 28
CIP29 CIP28
R/W-0 R/W-0
21 20
CIP21 CIP20
R/W-0 R/W-0
13 12
CIP13 CIP12
R/W-0 R/W-0
5 4
CIP5 CIP4
R/W-0 R/W-0
† Value Description
0−FFFF FFFFh Channel 0−31 interrupt pending. When the TCINT or ATCINT
bit in the channel options parameter (OPT) is set to 1 for an
EDMA channel and a specific transfer complete code (TCC)
or alternate transfer complete code (ATCC) is provided by the
EDMA transfer controller, the EDMA channel controller sets a
bit in the CIP field.
0 EDMA channel interrupt is not pending.
1 EDMA channel interrupt is pending.
27 26
CIP27 CIP26
R/W-0 R/W-0
19 18
CIP19 CIP18
R/W-0 R/W-0
11 10
CIP11 CIP10
R/W-0 R/W-0
3 2
CIP3 CIP2
R/W-0 R/W-0
25 24
CIP25 CIP24
R/W-0 R/W-0
17 16
CIP17 CIP16
R/W-0 R/W-0
9 8
CIP9 CIP8
R/W-0 R/W-0
1 0
CIP1 CIP0
R/W-0 R/W-0
SPRU234B