Mmc Interrupt Mask Register (Mmcim); Mmc Interrupt Mask Register (Mmcim) Field Descriptions - Texas Instruments TMS320DM644x User Manual

Registers
4.5

MMC Interrupt Mask Register (MMCIM)

The MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) status interrupts.
If an interrupt is enabled, the transition from 0 to 1 of the corresponding interrupt bit in the MMC status
register 0 (MMCST0) can cause an interrupt signal to be sent to the CPU.
The MMC interrupt mask register (MMCIM) is shown in
31
15
Reserved
R-0
7 6
ECRCRS ECRCRD
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions
Bit Field Value
31-13 Reserved 0
12 ETRNDNE
0
1
11 EDATED
0
1
10 EDRRDY
0
1
9 EDXRDY
0
1
8 Reserved 0
7 ECRCRS
0
1
6 ECRCRD
0
1
5 ECRCWR
0
1
4 ETOUTRS
0
1
46 Multimedia Card (MMC)/Secure Digital (SD) Card Controller
Figure 22. MMC Interrupt Mask Register (MMCIM)
Reserved
13 12
ETRNDNE
R/W-0
5 4
ECRCWR ETOUTRS
R/W-0 R/W-0
Description
Reserved
Transfer done (TRNDNE) interrupt enable.
Transfer done interrupt is disabled.
Transfer done interrupt is enabled.
DAT3 edge detect (DATED) interrupt enable.
DAT3 edge detect interrupt is disabled.
DAT3 edge detect interrupt is enabled.
Data receive register ready (DRRDY) interrupt enable.
Data receive register ready interrupt is disabled.
Data receive register ready interrupt is enabled.
Data transmit register (MMCDXR) ready interrupt enable.
Data transmit register ready interrupt is disabled.
Data transmit register ready interrupt is enabled.
Reserved
Response CRC error (CRCRS) interrupt enable.
Response CRC error interrupt is disabled.
Response CRC error interrupt is enabled.
Read-data CRC error (CRCRD) interrupt enable.
Read-data CRC error interrupt is disabled.
Read-data CRC error interrupt is enabled.
Write-data CRC error (CRCWR) interrupt enable.
Write-data CRC error interrupt is disabled.
Write-data CRC error interrupt is disabled.
Response time-out event (TOUTRS) interrupt enable.
Response time-out event interrupt is disabled.
Response time-out event interrupt is enabled.
Figure 22 and described in
R-0
11 10
EDATED EDRRDY
R/W-0 R/W-0
3 2
ETOUTRD ERSPDNE
R/W-0 R/W-0
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Table 10.
16
9 8
EDXRDY Reserved
R/W-0 R-0
1 0
EBSYDNE EDATDNE
R/W-0 R/W-0
SPRUE30B – September 2006
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