Intel 8XC251SA User Manual page 85

Memory
200H 201H
Register File
A3H
Contents of register file and memory after execution
Figure 5-1. Word and Double-word Storage in Big Endien Form
Table 5-2. Notation for Byte Registers, Word Registers, and Dword Registers
Register Register
Type Symbol
Ri
Byte Rn
Rm
Word WRj
Dword DRk
Instructions in the MCS 51 architecture use 80H–FFH as addresses for both memory locations
and SFRs, because memory locations are addressed only indirectly and SFR locations are ad-
dressed only directly. For compatibility, software tools for MCS 251 controllers recognize this
notation for instructions in the MCS 51 architecture. No change is necessary in any code written
for MCS 51 controllers.
For new instructions in the MCS 251 architecture, the memory region prefixes (00:, 01, ..., FF:)
and the SFR prefix (S:) are required. Also, software tools for the MCS 251 architecture permit
00: to be used for memory addresses 00H–FFH and permit the prefix S: to be used for SFR ad-
dresses in instructions in the MCS 51 architecture.
202H 203H
A3H B6H
0 1 2 3
B6H
WR0
Destination Source
Register Register
—
—
Rmd
WRjd
DRkd
MOV WR0,#A3B6H
MOV 00:0201H,WR0
MOV DR4,#0000C4D7H
4 5 6
00H 00H C4H
DR4
Register Range
— R0, R1
— R0–R7
Rms R0–R15
WRjs WR0, WR2, WR4, ..., WR30
DRks DR0, DR4, DR8, ..., DR28, DR56, DR60
PROGRAMMING
7
D7H
A4242-01
5-3