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Logical AND
Logical OR
Logical Exclusive OR
Clear
Complement
Rotate
Shift
SWAP
Mnemonic
<dest>,<src>
A,Rn
A,dir8
A,@Ri
A,#data
dir8,A
dir8,#data
Rmd,Rms
ANL;
WRjd,WRjs
ORL;
Rm,#data
XRL;
WRj,#data16
Rm,dir8
WRj,dir8
Rm,dir16
WRj,dir16
Rm,@WRj
Rm,@DRk
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
Rm
SLL
WRj
NOTES:
1.
See section A.4, "Instruction Descriptions."
2.
A shaded cell denotes an instruction in the MCS
3.
If this instruction addresses an I/O port (P x , x = 0–3), add 1 to the number of states.
4.
If this instruction addresses an I/O port (P x , x = 0–3), add 2 to the number of states.
Table A-23. Summary of Logical Instructions
ANL <dest>,<src>
ORL <dest>,<src>
XRL <dest>,<src>
CLR A
CPL A
RXX A
SXX Rm or Wj
A
Notes
Reg to acc
Dir byte to acc
Indir addr to acc
Immediate data to acc
Acc to dir byte
Immediate data to dir byte
Byte reg to byte reg
Word reg to word reg
8-bit data to byte reg
16-bit data to word reg
Dir addr to byte reg
Dir addr to word reg
Dir addr (64K) to byte reg
Dir addr (64K) to word reg
Indir addr (64K) to byte reg
Indir addr (16M) to byte reg
Clear acc
Complement acc
Rotate acc left
Rotate acc left through the carry
Rotate acc right
Rotate acc right through the carry
Shift byte reg left
Shift word reg left
INSTRUCTION SET REFERENCE
dest opnd ←dest opnd Λ src opnd
dest opnd ← dest opnd V src opnd
dest opnd ← dest opnd ∀ src opnd
(A) ← 0
(Ai) ← Ø(Ai)
(1)
(1)
A3:0 ↔ A7:4
Binary Mode
Bytes States Bytes States
1
2
1
2
2
3
3
3
4
5
4
4
5
5
4
4
1
1
1
1
1
1
3
3
®
51 architecture.
Source Mode
1
2
2
1 (3)
2
1 (3)
2
2
3
1
2
1
2 (4)
2
2 (4)
3 (4)
3
3 (4)
2
2
1
3
2
2
3
3
2
4
4
3
3 (3)
3
2 (3)
4
3
3
3
4
2
4
4
3
3
3
2
4
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
1
A-17
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